变量在verilog中是什么意思? [英] What does |variable mean in verilog?

问题描述

我想知道assign hd_trs_detected = |hd_trs_match;在verilog中是什么意思.我对|hd_trs_match部分最感兴趣.我知道表示按位或，但不确定如何在|之前没有值的情况下解释它.它是可以理解的"1"还是"0"?如果它为0，那么使用|hd_trs_match而不是仅使用hd_trs_match作为hd_trs_detected的优势将始终是什么hd_trs_match is?或者它本身可能是一个明智的操作.

I am wondering what assign hd_trs_detected = |hd_trs_match; means in verilog. I am mostly interested in the |hd_trs_match part. I know that | means bit wise OR, but not sure how to interpret it without a value before the |. Is it an understood '1' or '0'? If it is a '0', what would be the advantage of using |hd_trs_match vs. just hd_trs_match as hd_trs_detected would always be whatever hd_trs_match is? Or could it be a bit wise operation of itself.

推荐答案

|是归约运算符.对于多位信号，它将产生将操作数应用于向量的每一位的输出.

The | is a reduction operator. For a multi-bit signal, it produces an output applying the operand to each bit of the vector.

例如，

wire [3:0] in;
wire out;
assign out = |in; // the same as out = in[3] | in[2] | in[1] | in[0];

您可以对&，^等进行相同的操作.

You can do the same with &, ^, etc.

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