#`DEL 在 Verilog 中是什么意思? [英] What does #`DEL mean in Verilog?

问题描述

我看到以下形式的一些陈述.#`DEL 在这里是什么意思?我无法轻易找到它的含义，因为它包含一个特殊字符.

I saw some statements in the form of below. What does #`DEL mean here? I cannot find its meaning easily because it contains a special character.

cmd <= #`DEL 32'b0

推荐答案

这是一个延迟声明.

将右侧的赋值延迟到左侧定义的量，在这种情况下延迟 cmd 变为零.

Delaying the assign of value on the Righthand side to the lefthand side by the defined amount, in this case delaying cmd becoming zero.

可以以任何时间或实时格式指定延迟，#1 将是 ...

The delay can be specified in any time or realtime format, #1 would be 1 timestep as defined by the ...

#1ns、#1us、#1ms 等在 SystemVerilog 中可用.

#1ns, #1us, #1ms and more are available in SystemVerilog.

更典型的情况是右手边不固定.

A more typical case would be with a non-constant right hand side.

assign a = #1ns b;

这里 a 将滞后 b 1 ns.

Here a will lag b by 1 ns.

可以在语言参考手册 LRM 通过搜索delay_value".

Reference to this can be found in Language Reference Manual LRM by searching for 'delay_value'.

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