Verilog问号(?)运算符 [英] Verilog question mark (?) operator

问题描述

我正在尝试将Verilog程序转换为VHDL，并且偶然发现一条语句，其中在Verilog程序中使用了问号(?)运算符.

I'm trying to translate a Verilog program into VHDL and have stumbled across a statement where a question mark (?) operator is used in the Verilog program.

以下是Verilog代码；

The following is the Verilog code;

1  module music(clk, speaker);
2  input clk;
3  output speaker;
4  parameter clkdivider = 25000000/440/2;

5  reg [23:0] tone;
6  always @(posedge clk) tone <= tone+1;

7  reg [14:0] counter;
8  always @(posedge clk) if(counter==0) counter <= (tone[23] ? clkdivider-1 : clkdivider/2-1); else counter <= counter-1;

9  reg speaker;
10  always @(posedge clk) if(counter==0) speaker <= ~speaker;
11  endmodule

我不理解第八行，请问有人可以阐明这一点吗? 我在asic-world网站上读到，问号是Z字符的Verilog替代词.但是我不明白为什么要在这种情况下使用它.

I don't understand the 8th line, could anyone please shed some light on this? I've read on the asic-world website that the question mark is the Verilog alternate for the Z character. But I don't understand why it's being used in this context.

亲切的问候

推荐答案

这是三元运算符.这是if语句的简写

That's a ternary operator. It's shorthand for an if statement

格式:

condition ? if true : if false

示例:

tone[23] ? clkdivider-1 : clkdivider/2-1

翻译成类似的东西(语法不正确，但我想您会理解的):

Translates to something like (not correct syntax but I think you'll get it):

if tone[23] is 1, counter = clkdivider-1
else counter = clkdivider/2-1

以下是使用if语句和三进制的 2比1 MUX的两个示例运算符.

Here are two examples of a 2 to 1 MUX using if statement and ternary operator.

在asic-world网站上，有条件的运营商

On the asic-world website, it is covered under Conditional Operators

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