汇编寄存器采用64位架构 [英] Assembly registers in 64-bit architecture

问题描述

按照

请参见新的X86_64处理器寄存器的名称是什么？

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关于呼叫约定，在特定系统上，仅一个约定 ¹ 。

• 在Windows上：

  
  
  
  
  
  • 前四个整数的RCX，RDX，R8，R9或指针参数
  
  
  • 浮点参数的XMM0，XMM1，XMM2，XMM3
  
  
  
  
  

  
  ¹ 自MSVC 2013起，Windows上还有一个新的扩展约定，称为 __ vectorcall ，因此单一约定策略不再适用。




• 在Linux和其他遵循系统V AMD64 ABI 的系统上 ，则可以在寄存器上传递更多参数，并且下面有一个128字节的红色区域

  
  
  
  
  
  • 前六个整数或指针参数为传递给寄存器RDI，RSI，RDX，RCX，R8和R9
  
  
  • 浮点参数通过XMM7传递给XMM0
  
  
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有关更多信息，请阅读 x86-64 和 x86-64调用约定

计划9中也使用了约定其中

• 所有寄存器都保存了呼叫者


• 所有参数都在堆栈上传递


• 返回值也返回到堆栈上，在下面保留的空间中（堆栈方式；

实际上，计划9始终是一个怪人。例如，在没有硬件零寄存器的RISC架构上，它强制寄存器为0。 x86寄存器上的名称在16位，32位和64位x86架构上也是一致的，其操作数大小由助记符后缀指示。这意味着ax可以是16位，32位或64位寄存器，具体取决于指令后缀。如果您对此感到好奇，请阅读

• 计划9汇编程序手册


• Go / plan9的汇编器很奇怪

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OTOH Itanium 是完全不同的体系结构，并且与x86-64无关。它是纯64位架构，因此所有普通寄存器都是64位，没有32位或更小版本。其中有很多寄存器：

• 128个通用整数寄存器r0至r127，每个寄存器64个值位和一个陷阱位。


• 128个浮点寄存器f0至f127。


• 64个谓词寄存器p0至p63。
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• 8个分支寄存器从b0到b7。


• 一个指令指针，Windows调试引擎出于某种原因将其称为iip。 （额外的 i代表疯狂吗？）


• 128个专用寄存器，并非所有寄存器都被赋予了含义。由于某种原因，这些被称为应用程序寄存器（ar）。在讨论过程中，我将介绍选定的寄存器。


• 本系列中将不介绍的其他杂项寄存器。

Itanium处理器，第1部分：热身

有关x64和IA-64有什么区别？

Following the answer about assembly registers' sizes:

• First, what sizes are eax, ax, ah and their counterparts, in the 64-bit architecture? How to access a single register's byte and how to access all the 64-bit register's eight bytes?

  I'd love attention for both x86-64 (x64) and Itanium processors.

• Second, what is the correct way to use the four registers for holding the first four parameters in function calls in the new calling convention?

解决方案

With the old names all registers remain the same size, just like when x86-16 was extended to x86-32. To access 64-bit registers you use the new names with R-prefix such as rax, rbx...

Register names don't change so you just use the byte registers (al, bl, cl, dl, ah, bh, ch, dh) for the LSB and MSB of ax, bx, cx, dx like before.

There are also 8 new registers called r8-r15. You can access their LSBs by adding the suffix b (or l if you're using AMD). For example r8b, r9b... You can also use the LSB of esi, edi, esp, ebp by the names sil, dil, spl, bpl with the new REX prefix, but you cannot use it at the same time with ah, bh, ch or dh.

Likewise the new registers' lowest word or double word can be accessed through the suffix w or d.

See What are the names of the new X86_64 processors registers?

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Regarding the calling convention, on a specific system there's only one convention¹.

• On Windows:

  • RCX, RDX, R8, R9 for the first four integer or pointer arguments
  • XMM0, XMM1, XMM2, XMM3 for floating-point arguments

  
  ¹Since MSVC 2013 there's also a new extended convention on Windows called __vectorcall so the "single convention policy" is not true anymore.

• On Linux and other systems that follow System V AMD64 ABI, more arguments can be passed on registers and there's a 128-byte red zone below the stack which may make function calling faster.

  • The first six integer or pointer arguments are passed in registers RDI, RSI, RDX, RCX, R8, and R9
  • Floating-point arguments are passed in XMM0 through XMM7

For more information should read x86-64 and x86-64 calling conventions

There's also a convention used in Plan 9 where

• All registers are caller-saved
• All parameters are passed on the stack
• Return values are also returned on the stack, in space reserved below (stack-wise; higher addresses on amd64) the arguments.

In fact Plan 9 was always a weirdo. For example it forces a register to be 0 on RISC architectures without a hardware zero register. x86 register names on it are also consistent across 16, 32 and 64-bit x86 architectures with operand size indicated by mnemonic suffix. That means ax can be a 16, 32 or 64-bit register depending on the instruction suffix. If you're curious about it read

• A Manual for the Plan 9 assembler
• Go/plan9’s assembler is weird

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OTOH Itanium is a completely different architecture and has no relation to x86-64 whatsoever. It's a pure 64-bit architecture so all normal registers are 64-bit, no 32-bit or smaller version is available. There are a lot of registers in it:

• 128 general-purpose integer registers r0 through r127, each carrying 64 value bits and a trap bit. We'll learn more about the trap bit later.
• 128 floating point registers f0 through f127.
• 64 predicate registers p0 through p63.
• 8 branch registers b0 through b7.
• An instruction pointer, which the Windows debugging engine for some reason calls iip. (The extra "i" is for "insane"?)
• 128 special-purpose registers, not all of which have been given meanings. These are called "application registers" (ar) for some reason. I will cover selected register as they arise during the discussion.
• Other miscellaneous registers we will not cover in this series.

The Itanium processor, part 1: Warming up

Read more on What is the difference between x64 and IA-64?

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