64 位架构中的汇编寄存器 [英] Assembly registers in 64-bit architecture
问题描述
遵循
<小时>关于调用约定，在特定系统上只有一个约定1.
- RCX、RDX、R8、R9 用于前四个整数或指针参数
- 用于浮点参数的 XMM0、XMM1、XMM2、XMM3
1自 MSVC 2013 起，Windows 上还有一个新的扩展约定，名为__vectorcall所以单一约定政策"不再适用.在 Linux 和其他遵循 System V AMD64 ABI 的系统上，可以传递更多参数在寄存器上，堆栈下方有一个 128 字节的红色区域，可能会进行函数调用更快.
- 前六个整数或指针参数在寄存器 RDI、RSI、RDX、RCX、R8 和 R9 中传递
- 浮点参数在 XMM0 到 XMM7 中传递
有关更多信息，请阅读 x86-64 和 x86-64 调用约定
计划 9 中还有一个约定，其中
<块引用>- 所有寄存器都是调用者保存的
- 所有参数都在栈上传递
- 返回值也在堆栈上返回，在参数下方(堆栈方式；amd64 上的更高地址)保留的空间中.
事实上，Plan 9 一直是个怪人.例如，它在没有硬件零寄存器的 RISC 架构上强制寄存器为 0.其上的 x86 寄存器名称在 16、32 和 64 位 x86 体系结构中也是一致的，操作数大小由助记符后缀指示.这意味着 ax 可以是 16、32 或 64 位寄存器，具体取决于指令后缀.如果您对此感到好奇，请阅读
<小时>OTOH Itanium 是一种完全不同的架构，并且具有与 x86-64 没有任何关系.它是一个纯 64 位架构，所以所有普通寄存器都是 64 位，没有 32 位或更小的版本可用.里面有很多寄存器:
<块引用>- 128 个通用整数寄存器 r0 到 r127，每个寄存器承载 64 个值位和一个陷阱位.我们稍后会详细了解陷阱.
- 128 个浮点寄存器 f0 到 f127.
- 64 个谓词寄存器 p0 到 p63.
- 8 个分支寄存器 b0 到 b7.
- 一个指令指针，Windows 调试引擎出于某种原因将其称为 iip.(额外的i"代表疯狂"?)
- 128 个特殊用途的寄存器，并不是所有的都被赋予了含义.出于某种原因，这些被称为应用程序寄存器"(ar).我将介绍讨论期间出现的选定寄存器.
- 我们不会在本系列中介绍的其他杂项寄存器.
Following the answer about assembly registers' sizes:
First, what sizes are
eax,ax,ahand their counterparts, in the 64-bit architecture? How to access a single register's byte and how to access all the 64-bit register's eight bytes?I'd love attention for both x86-64 (x64) and Itanium processors.
Second, what is the correct way to use the four registers for holding the first four parameters in function calls in the new calling convention?
With the old names all registers remain the same size, just like when x86-16 was extended to x86-32. To access 64-bit registers you use the new names with R-prefix such as rax, rbx...
Register names don't change so you just use the byte registers (al, bl, cl, dl, ah, bh, ch, dh) for the LSB and MSB of ax, bx, cx, dx like before.
There are also 8 new registers called r8-r15. You can access their LSBs by adding the suffix b (or l if you're using AMD). For example r8b, r9b... You can also use the LSB of esi, edi, esp, ebp by the names sil, dil, spl, bpl with the new REX prefix, but you cannot use it at the same time with ah, bh, ch or dh.
Likewise the new registers' lowest word or double word can be accessed through the suffix w or d.
See What are the names of the new X86_64 processors registers?
Regarding the calling convention, on a specific system there's only one convention1.
-
- RCX, RDX, R8, R9 for the first four integer or pointer arguments
- XMM0, XMM1, XMM2, XMM3 for floating-point arguments
1Since MSVC 2013 there's also a new extended convention on Windows called__vectorcallso the "single convention policy" is not true anymore. On Linux and other systems that follow System V AMD64 ABI, more arguments can be passed on registers and there's a 128-byte red zone below the stack which may make function calling faster.
- The first six integer or pointer arguments are passed in registers RDI, RSI, RDX, RCX, R8, and R9
- Floating-point arguments are passed in XMM0 through XMM7
For more information should read x86-64 and x86-64 calling conventions
There's also a convention used in Plan 9 where
- All registers are caller-saved
- All parameters are passed on the stack
- Return values are also returned on the stack, in space reserved below (stack-wise; higher addresses on amd64) the arguments.
In fact Plan 9 was always a weirdo. For example it forces a register to be 0 on RISC architectures without a hardware zero register. x86 register names on it are also consistent across 16, 32 and 64-bit x86 architectures with operand size indicated by mnemonic suffix. That means ax can be a 16, 32 or 64-bit register depending on the instruction suffix. If you're curious about it read
OTOH Itanium is a completely different architecture and has no relation to x86-64 whatsoever. It's a pure 64-bit architecture so all normal registers are 64-bit, no 32-bit or smaller version is available. There are a lot of registers in it:
- 128 general-purpose integer registers r0 through r127, each carrying 64 value bits and a trap bit. We'll learn more about the trap bit later.
- 128 floating point registers f0 through f127.
- 64 predicate registers p0 through p63.
- 8 branch registers b0 through b7.
- An instruction pointer, which the Windows debugging engine for some reason calls iip. (The extra "i" is for "insane"?)
- 128 special-purpose registers, not all of which have been given meanings. These are called "application registers" (ar) for some reason. I will cover selected register as they arise during the discussion.
- Other miscellaneous registers we will not cover in this series.
Read more on What is the difference between x64 and IA-64?
这篇关于64 位架构中的汇编寄存器的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
