为什么这个任务不明确？ [英] Why is this assignment ambiguous?

问题描述

请注意，此问题不是关于如何更改以下代码以使其起作用；相反，我正在寻找有关为什么编译器会发现此赋值模棱两可的一些见解：

Please note that this question is not about how to change the code below to make it work; rather, I am looking for some insight on why a compiler would find this assignment ambiguous:

entity assignment_to_aggregates is
end;

architecture example of assignment_to_aggregates is
    type vowel_type is (a, e, i, o, u);
    type consonant_type is (b, c, d, f, g);
    type vowel_consonant_pair is record
        vowel: vowel_type;
        consonant: consonant_type;
    end record;

    signal my_vowel: vowel_type;
    signal my_consonant: consonant_type;
begin
    (my_vowel, my_consonant) <= (a, b); -- Doesn't work: "Ambiguous types in signal assignment statement."
end;

我已经使用Modelsim Altera 10.1b和GHDL 0.29.1对它进行了测试，并且看到了以下内容错误消息：

I have tested it with Modelsim Altera 10.1b and GHDL 0.29.1 and I'm seeing the following error messages:

VCOM: (vcom-1349) Ambiguous types in signal assignment statement
    Possible target types are:
        vowel_consonant_pair
        ieee.std_logic_1164.STD_ULOGIC_VECTOR
        std.STANDARD.TIME_VECTOR
        std.STANDARD.REAL_VECTOR
        std.STANDARD.INTEGER_VECTOR
        std.STANDARD.BIT_VECTOR
        std.STANDARD.BOOLEAN_VECTOR
        std.STANDARD.STRING

GHDL: type of waveform is unknown, use type qualifier

当然，如果我显式声明一个新类型（示例代码中的 vowel_consonant_pair ）并使用类型限定，则可以正常工作：

Of course, if I declare a new type explicitly (vowel_consonant_pair in the sample code) and use type qualification, it works fine:

(my_vowel, my_consonant) <= vowel_consonant_pair'(a, b); -- Works fine

但是，如果绝对没有其他类型可以匹配，为什么要这样做作业右侧的汇总？这是工具问题，还是VHDL语义问题？如果是后者，请问有人可以提供LRM参考吗？

But why should this be necessary, if there is absolutely no other type that could match the aggregate on the right-hand side of the assignment? Is this a tool problem, or is this a VHDL semantics problem? If the latter, could someone please provide a LRM reference?

推荐答案

引自我对上一个问题的回答：

Quoted from my answer to the previous question:

IEEE Std 1076-1993，8.4信号分配声明（请参见-2008，10.5 / 10.5.2.1）：

IEEE Std 1076-1993, 8.4 Signal assignment statement (see -2008, 10.5/10.5.2.1):

如果信号分配语句的目标是
聚合的形式，则聚合的类型必须可以从
的上下文中确定，不包括聚合本身，但包括事实
聚合的类型必须是复合类型。

If the target of the signal assignment statement is in the form of an aggregate, then the type of the aggregate must be determinable from the context, excluding the aggregate itself but including the fact that the type of the aggregate must be a composite type.

再添加一点：

-1993，0.2本文档的结构和术语（请参见-2008，1.3 / 1.3.1：

-1993, 0.2 Structure and terminology of this document (see -2008, 1.3/1.3.1:

另外，单词 must用来表示强制重量
这个单词比更常见的 shall更可取，因为 must表示
a对本标准的不同读者来说是不同的意思。

Additionally, the word "must" is used to indicate mandatory weight. This word is preferred over the more common "shall," as "must" denotes a different meaning to different readers of this standard.

这是一种语义限制，必须具有强制性的权重，否则必须满足的条件才会在VHDL中产生错误。没有限定条件就无法知道聚合的类型。请注意，在标准的2008年版本中，必须已由必须代替。

It's a semantic restriction, 'must' carries a mandatory weight, a condition that must be met will otherwise generate and error in VHDL. The type of the aggregate isn't known without qualification. Note 'that' must has been supplanted by 'shall' in the 2008 version of the standard.

此处讨论的类型是目标（左侧） 。我们受并发信号分配部分的第一句 IEEE Std 1076-2008中有关并发信号分配语句的顺序信号分配部分中的要求的约束：

The type in question here is of the target (the left hand side). We're bound by to the requirement in the section on sequential signal assignment for the concurrent signal assignment statement by the first sentence of the section on concurrent signal assignment, IEEE Std 1076-2008:

11.6并发信号分配语句

11.6 Concurrent signal assignment statements

并发信号分配语句代表等效的
过程语句，该过程语句为信号分配值

A concurrent signal assignment statement represents an equivalent process statement that assigns values to signals.

（也在-1993，9.5中找到）。

(Also found in -1993, 9.5).

类型通常作为名称的属性携带，但聚合不是命名对象。可以从右侧获取类型，除了它也是一个总计：

Type is generally carried as an attribute on a name, but the aggregate isn't a named object. It's possible to get the type from the right hand side except it's an aggregate too:

(my_vowel, my_consonant) <= (a, b);

尼克·加森（Nick Gasson）的VHDL分析仪/模拟器nvc更加优雅地指出了解决问题的地方：

Nick Gasson's VHDL analyzer/simulator nvc points a little more elegantly to where to fix the problem:

nvc -a assignment_to_aggregate.vhdl  
** Error: no composite type in context
      File assignment_to_aggregate.vhdl, Line 11  
        (my_vowel, my_consonant) <= (a,b);  
                                    ^^^^^

（针对由缺少使用先前的stackoverflow VHDL问题发现的语义检查）。

(Following a fix for an elaboration 'crash' caused by a missing semantic check found using a previous stackoverflow VHDL question).

如何键入右侧？

摘自IEEE标准1076-1993：

From IEEE Std 1076-1993:

7.3.4合格表达式

7.3.4 Qualified expressions

限定表达式是基本操作（请参阅第3节
的介绍），用于显式声明类型，可能还可以声明
子类型

A qualified expression is a basic operation (see the introduction to Section 3)that is used to explicitly state the type, and possibly the subtype, of an operand that is an expression or an aggregate.

 qualified_expression ::=
        type_mark ' ( expression )
      | type_mark ' aggregate

操作数必须与类型标记的基本类型相同。
限定表达式的值是操作数的值。
对合格表达式的求值将对操作数求值并检查
其值是否属于类型标记所表示的子类型。

The operand must have the same type as the base type of the type mark. The value of a qualified expression is the value of the operand. The evaluation of a qualified expression evaluates the operand and checks that its value belongs to the subtype denoted by the type mark.

注意-每当从上下文中不知道枚举文字或总计的类型
时，都可以使用限定表达式明确声明
的类型。

NOTE--Whenever the type of an enumeration literal or aggregate is not known from the context, a qualified expression can be used to state the type explicitly.

在任何VHDL标准版本中都没有术语表的定义。
一个有效的定义可能包括这样的概念，即某事物的声明是可见的，而没有限定条件的集合类型则不是这种情况。

There isn't a glossary definition of 'context' in any of the VHDL standard versions. A working definition might include the notion that the declaration for something is visible, which isn't the case for the type of an aggregate without qualification.

I将 answer 写为在前面的问题中，我专门介绍了记录类型声明，以解决在合格的表达式中用类型标记修饰聚合的能力不足。请注意，没有声明为vowel_consonant_pair记录的子类型（信号和）。还需要类型声明，而不是实际记录。

I wrote the answer to the previous question and I introduced the record type declaration specifically to address the lack of ability to decorate the aggregate with a type mark in a qualified expression. Note that there is no subtype (signal and) declared as a vowel_consonant_pair record. The type declaration was needed, not an actual record.

还请注意，我在ghdl-0.31上提交了一个错误，该错误已被固定为源代码树，但是没有实际的记录。发布--当无法识别聚合类型时 ghdl barfs 。如果您不使用该表达式，则新版本的ghdl不会崩溃。

Also note I submitted a bug on ghdl-0.31 which has been fixed source tree but there hasn't been an actual release since - ghdl barfs when it can't discern the type of an aggregate. A newer version of ghdl won't crash if you don't qualify the expression.

关于stackoverflow的问题通常对改进开源VHDL工具做出了杰出的贡献。

Questions on stackoverflow generally make a wonderful contribution to improving open source VHDL tools.

我会很方便地使用标准，通常能够引用章节。可能需要做很多工作，尽管没有置换索引，但通过透彻阅读标准几乎无法了解VHDL，您必须灌输术语以了解您所要表达的意义。

I keep the standards handy and usually am able to cite chapter and verse. It can be a lot of work, there's very little you can't find out about VHDL by a thorough reading of the standard although there isn't a permuted index and you have to be inculcated in the terminology to understand the significance of what you read.

就像您当前问题的答案一样，标准中的引用可以导致标准的另一部分。

Like the answer to your current question a reference in the standard can lead to another part of the standard.

Jim Lewis引用的comp.lang.vhdl FAQ 在最近的答案中是一个很好的参考，但有时很少使用-1993标准的参考。

The comp.lang.vhdl FAQ quoted by Jim Lewis in a recent answer is a wonderful reference but sometimes lacks authoritative emphasis, using references to the -1993 standard sparingly.

请参阅FAQ， 4.2.18如何解决表达式中的类型歧义。

您的困惑似乎源于Modelsim错误消息，提示出现解决歧义所需要的可能类型。请注意4.2.18中的第一句话：

Your confusion seems to stem from the Modelsim error messages suggesting 'possible' types needed to resolve ambiguity. Note the first sentence in the 4.2.18:

VHDL是一种强类型语言。因此，编译器不会
执行任何隐式类型转换或尝试猜测表达式的类型
。

VHDL is a strongly typed language. Hence, the compiler does not perform any implicit type conversions or attempt to "guess" the type of an expression.

并且聚合是一个表达式（请参见7.3.2 / 9.3.3聚合，-1993 / -2008）。

And an aggregate is an expression (See 7.3.2/9.3.3 Aggregates, -1993/-2008).

提供了大多数可能的类型声明由vcom errror消息发出的消息对于由两个不同的类型元素组成的集合来说是不准确的-a是vowel_type值的枚举名称，b是consonant_type值的枚举。

Most of the possible type declarations provided by the vcom errror message are not accurate for the aggregate which is comprised of two disparate type elements - a is an enumeration name for a value of vowel_type and b is an enumeration for a value of consonant_type.

vcom错误提供的类型似乎是通过本地声明（vowel_consonant_pair）或上下文子句（std_ulogic_vector，real_vector，integer_vector，bit_vector，boolean_vector，字符串，在ieee.std_logic_1164中共同可见）显示的所有复合类型

The types provided with the vcom error appear to be all the composite types made visible by local declaration (vowel_consonant_pair) or context clause (std_ulogic_vector, real_vector, integer_vector, bit_vector, boolean_vector, string, collectively found in ieee.std_logic_1164 or std.standard).

在那一堆中，只有一个是有效的（vowel_consonant_pair）。请注意，VHDL分析器没有猜测，而是要求根据语义规则（信号分配语句8.4 / 10.5.2.1， ... then）从上下文中提供正确的类型作为对象修饰（类型限定）。聚合的类型必须从上下文中确定，不包括聚合本身，但包括聚合的类型必须是复合类型这一事实）。该规则给出了可能的候选者列表，可用的复合类型，同时不允许进行猜测（不包括聚合本身）。

Of that bunch only one would be valid (vowel_consonant_pair). Notice the VHDL analyzer didn't guess, instead requiring the correct type to be made available from context as an object decoration (type qualification) as a result of a semantic rule (Signal assignment statement 8.4/10.5.2.1, "...the type of the aggregate must be determinable from the context, excluding the aggregate itself but including the fact that the type of the aggregate must be a composite type"). The rule giving the list of possible candidates, available composite types while disallowing guessing ("excluding the aggregate itself").

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