了解分支预测 [英] Understanding branch prediction

问题描述

有些关于分支预测的查询我无法自信地弄清楚。假设我必须使用静态分支预测器。

There are some queries about branch prediction that I am not able to confidently figure out.Assume that I have to work with a static branch predictor.

1. 分支预测应该在管道的哪个阶段发生？


2. 如何知道预测出错了？数据路径如何得知发生了错误预测？


3. 如果得知发生了错误的预测，它将如何发送信号占用未采用的分支？


4. 之后出了错，我必须处理以前没有用的那个地址。同时，如果发生了某些存储器写或寄存器写怎么办？如何防止它发生？

1. At which stage of the pipeline should branch prediction happen?
2. How to know that a prediction has gone wrong? How does the datapath come to know that a misprediction has happened?
3. If it comes to know that a misprediction has happened, how does it send the signal to take up the not-taken branch?
4. After it has gone wrong, I have to take up that address that was not taken earlier. In the meanwhile, what if some memory-write or register-write has happened? How to prevent it from happening?

即使某些适当的数据路径引用也将非常有帮助在他们建议。

It will be very helpful even if some proper references with datapath in them are suggested. Thanks in advance.

推荐答案

我花了一些时间阅读Cortex-A8的参考手册： http://infocenter.arm.com/help/topic/com.arm.doc。 ddi0344k / DDI0344K_cortex_a8_r3p2_trm.pdf

I took my time reading the reference manual for the Cortex-A8: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/DDI0344K_cortex_a8_r3p2_trm.pdf

从5.1节开始：

处理器包含程序流预测硬件，也称为
分支预测。在禁用程序流预测的情况下，所有采取的
分支都将遭受13个周期的罚款。启用程序流预测
后，所有错误预测的分支都会产生13个周期的罚款。

The processor contains program flow prediction hardware, also known as branch prediction. With program flow prediction disabled, all taken branches incur a 13-cycle penalty. With program flow prediction enabled, all mispredicted branches incur a 13-cycle penalty.

基本上，这意味着静态分支预测始终假设分支为假。与PowerPC相比，后者具有特殊指令来提示处理器有关已采用/未采用分支的信息（后缀+/-）。

Basically this means that static branch prediction always assume branches to be false. This is different compared to PowerPC that have "special instructions" for hinting the processor about taken/not-taken branches (postfix +/-).

来自1.3.1节：

指令获取单元预测指令流，从L1指令高速缓存中获取
指令，并将获取的$ b放入$ b指令进入缓冲区供解码管道使用。

The instruction fetch unit predicts the instruction stream, fetches instructions from the L1 instruction cache, and places the fetched instructions into a buffer for consumption by the decode pipeline.

1. 指令提取，第一阶段，做出预测。

从7.6.2节开始：

一条指令可以保留在获取和执行
之间的流水线中。因为
的管道中可能有几个未解决的分支，所以指令提取是推测性的，这意味着
不能保证它们会被执行。代码流中的分支或特殊
指令可能导致流水线刷新，从而丢弃当前获取的指令。在没有空管道的情况下开始的获取或指令
表游标被标记为
具有推测性。如果管道包含直到
分支和异常解析点为止的任何指令，则该管道为
，认为不为空。

An instruction can remain in the pipeline between being fetched and being executed. Because there can be several unresolved branches in the pipeline, instruction fetches are speculative, meaning there is no guarantee that they are executed. A branch or exceptional instruction in the code stream can cause a pipeline flush, discarding the currently fetched instructions. Fetches or instruction table walks that begin without an empty pipeline are marked speculative. If the pipeline contains any instruction up to the point of branch and exception resolution, then the pipeline is considered not empty.

我将其解释为在处理分支时没有任何东西到达执行阶段。如果发生错误迁移（如在执行指令执行中执行分支时发现的那样），则流水线中的所有指令都将清除。它们永远不会执行。那应该回答问题2和4。不确定如何执行标记。

I interpret this as nothing reaches the execution stage while a branch is being processed. If mispredition occurs, as discovered when executing a branch in Instruction Execute, all instructions in the pipeline are "flushed". They are never executed. That should answer question 2 and 4. Not so sure about how the "marking" is performed.

1. 我不知道不知道它如何发送信号。据我所知，参考手册并未涵盖该部分。猜猜它是神奇的。

（根据记录，我发现了PowerPC参考手册（e500 / e600）因为有很多指令时序样本，所以更容易理解。）

(For the record I find the PowerPC reference manuals (e500/e600) I´m used to being much easier to understand because of the many instruction timing samples.)

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