了解分支预测 [英] Understanding branch prediction

问题描述

有一些关于分支预测的问题，我无法确定.假设我必须使用静态分支预测器.

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1. 应该在流水线的哪个阶段进行分支预测?
2. 如何知道预测出错了?数据路径如何知道发生了错误预测?
3. 如果知道发生了错误预测，它如何发送信号以占用未采用的分支?
4. 出现问题后，我必须使用之前没有使用的地址.同时，如果发生了一些内存写入或寄存器写入怎么办?如何防止它发生?

即使建议了一些带有数据路径的适当引用，这也会非常有帮助.提前致谢.

解决方案

我花时间阅读了 Cortex-A8 的参考手册:http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/DDI0344K_cortex_a8_r3p2_trmp.pdf>

来自第 5.1 节:

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处理器包含程序流预测硬件，也称为分支预测.禁用程序流预测，全部采用分支会产生 13 个周期的惩罚.带程序流预测启用后，所有错误预测的分支都会受到 13 个周期的惩罚.

基本上这意味着静态分支预测总是假设分支为假.这与 PowerPC 不同，后者具有特殊指令"，用于提示处理器关于采用/未采用分支(后缀 +/-).

来自第 1.3.1 节:

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取指令单元预测指令流，取来自 L1 指令缓存的指令，并将获取的指令放入指令放入缓冲区供解码管道使用.

1. Instruction Fetch，第一阶段，进行预测.

来自第 7.6.2 节:

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一条指令可以在被获取和被提取之间保留在流水线中被处决.因为可能有几个未解决的分支管道，指令提取是推测性的，这意味着有不保证它们会被执行.分支或例外代码流中的指令会导致流水线刷新，丢弃当前获取的指令.获取或指令没有空管道的表走被标记投机.如果管道包含任何指令直到分支和异常解决的点，那么管道是认为不为空.

我将此解释为在处理分支时没有任何内容到达执行阶段.如果发生错误预测，如在指令执行中执行分支时发现的那样，管道中的所有指令都将被刷新".他们永远不会被处决.那应该回答问题 2 和 4.不太确定标记"是如何执行的.

3. 我不知道它是如何发送信号的.据我所知，参考手册不包括那部分.猜猜这是魔术.

(作为记录，我找到了 PowerPC 参考手册 (e500/e600)，因为有许多指令时序示例，我习惯于更容易理解.)

There are some queries about branch prediction that I am not able to confidently figure out.Assume that I have to work with a static branch predictor.

1. At which stage of the pipeline should branch prediction happen?
2. How to know that a prediction has gone wrong? How does the datapath come to know that a misprediction has happened?
3. If it comes to know that a misprediction has happened, how does it send the signal to take up the not-taken branch?
4. After it has gone wrong, I have to take up that address that was not taken earlier. In the meanwhile, what if some memory-write or register-write has happened? How to prevent it from happening?

It will be very helpful even if some proper references with datapath in them are suggested. Thanks in advance.

解决方案

I took my time reading the reference manual for the Cortex-A8: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/DDI0344K_cortex_a8_r3p2_trm.pdf

From section 5.1:

The processor contains program flow prediction hardware, also known as branch prediction. With program flow prediction disabled, all taken branches incur a 13-cycle penalty. With program flow prediction enabled, all mispredicted branches incur a 13-cycle penalty.

Basically this means that static branch prediction always assume branches to be false. This is different compared to PowerPC that have "special instructions" for hinting the processor about taken/not-taken branches (postfix +/-).

From section 1.3.1:

The instruction fetch unit predicts the instruction stream, fetches instructions from the L1 instruction cache, and places the fetched instructions into a buffer for consumption by the decode pipeline.

1. Instruction Fetch, the first stage, makes the prediction.

From section 7.6.2:

An instruction can remain in the pipeline between being fetched and being executed. Because there can be several unresolved branches in the pipeline, instruction fetches are speculative, meaning there is no guarantee that they are executed. A branch or exceptional instruction in the code stream can cause a pipeline flush, discarding the currently fetched instructions. Fetches or instruction table walks that begin without an empty pipeline are marked speculative. If the pipeline contains any instruction up to the point of branch and exception resolution, then the pipeline is considered not empty.

I interpret this as nothing reaches the execution stage while a branch is being processed. If mispredition occurs, as discovered when executing a branch in Instruction Execute, all instructions in the pipeline are "flushed". They are never executed. That should answer question 2 and 4. Not so sure about how the "marking" is performed.

3. I don´t know how it sends the signal. As far as I can tell the reference manual does not cover that part. Guess it´s magic.

(For the record I find the PowerPC reference manuals (e500/e600) I´m used to being much easier to understand because of the many instruction timing samples.)

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