VHDL流程与灵敏度列表的混淆 [英] VHDL Process Confusion with Sensitivity Lists

问题描述

我正在通过在线阅读书籍(自由范围VHDL)来学习VHDL，并通过Xilinx ISE Webpack 14.7在我的Nexsys2上实现示例.我正在重新阅读Free Range VHDL文本，目前正在讨论过程的这一章中.我对流程是什么以及它如何工作有深刻的了解，但是我实现了一个示例，但我不理解结果.

I am learning VHDL by reading books online (Free Range VHDL), and imlementing the examples on my Nexsys2 via Xilinx ISE Webpack 14.7. I am re-reading the Free Range VHDL text and am currently in the chapter discussing processes. I have a solid understanding of what a process is, and how it works, but I implemented an example and I do not understand the results.

我使用以下代码实现了8对1多路复用器.

I implemented an 8 to 1 mux using the following code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux81 is
    port( d_in : in std_logic_vector(7 downto 0);
            sel : in std_logic_vector(2 downto 0);
            ce : in std_logic;
            F : out std_logic);
end mux81;

architecture my_mux81 of mux81 is
begin
mux_proc: process(d_in, sel, ce)
    begin
        if (ce = '1') then
            if (sel = "111") then
                F <= d_in(7);
            elsif (sel = "110") then
                F <= d_in(6);
            elsif (sel = "101") then
                F <= d_in(5);
            elsif (sel = "100") then
                F <= d_in(4);
            elsif (sel = "011") then
                F <= d_in(3);
            elsif (sel = "010") then
                F <= d_in(2);
            elsif (sel = "001") then
                F <= d_in(1);
            elsif (sel = "000") then
                F <= d_in(0);
            else
                F <= '0';   
            end if;
        else
            F <= '0';
        end if;
    end process mux_proc;
end my_mux81;

仅在"ce"信号为"1"时执行多路复用操作.一切都按预期进行.然后，我通过从灵敏度列表中删除"ce"信号进行了尝试.根据我对过程语句的理解，仅当敏感度列表中的信号发生更改时，它才应执行.通过消除"ce"信号，电路不应单独响应"ce"变化.这是修改后的电路:

which performs the mux operation only if the 'ce' signal is '1'. All worked as expected. I then tried an experiment by removing the 'ce' signal from the sensitivity list. Based on my understanding of the process statement, it should only execute if a signal in the sensitivity list changes. By removing the 'ce' signal, the circuit should not respond to 'ce' changes alone. Here is the modified circuit:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux81 is
    port( d_in : in std_logic_vector(7 downto 0);
            sel : in std_logic_vector(2 downto 0);
            ce : in std_logic;
            F : out std_logic);
end mux81;

architecture my_mux81 of mux81 is
begin
mux_proc: process(d_in, sel)
    begin
        if (ce = '1') then
            if (sel = "111") then
                F <= d_in(7);
            elsif (sel = "110") then
                F <= d_in(6);
            elsif (sel = "101") then
                F <= d_in(5);
            elsif (sel = "100") then
                F <= d_in(4);
            elsif (sel = "011") then
                F <= d_in(3);
            elsif (sel = "010") then
                F <= d_in(2);
            elsif (sel = "001") then
                F <= d_in(1);
            elsif (sel = "000") then
                F <= d_in(0);
            else
                F <= '0';   
            end if;
        else
            F <= '0';
        end if;
    end process mux_proc;
end my_mux81;

如您所见，唯一的变化是从敏感度列表中删除了"ce".但是，当我实现该电路时，它的运行方式与灵敏度列表中带有"ce"的版本完全相同.换句话说，保持信号"d_in"和"sel"恒定，但修改"ce"会导致过程语句执行并更改输出信号，就好像"ce"仍在灵敏度列表中一样.进行综合操作时，我没有收到任何警告.就像程序假设"ce"也应受到监视一样，但我认为这也应产生警告...

As you can see, the only change is that 'ce' is removed from the sensitivity list. However, when I implement this circuit, it operates exactly like the version that had 'ce' in the sensitivity list. In other words, keeping signals "d_in" and "sel" constant, but modifying 'ce' caused the process statement to execute and change the output signal as if 'ce' were still in the sensitivity list. I did not get any warnings when I ran the synthesis. It is like the program made an assumption that 'ce' should also be monitored, but I thought that should also generate a warning...

感谢您的帮助！

推荐答案

灵敏度列表被许多综合工具所忽略.查看综合工具发出的警告，您可能会发现它警告缺少CE信号.

Sensitivity lists are ignored by many synthesis tools. Check the warnings from your synthesis tool, and you will probably find that it warns about the missing CE signal.

不完整的灵敏度列表是引起问题的一个臭名昭著的原因，因为模拟和合成后的行为并不相同！

Incomplete sensitivity lists are a notorious cause of problems, because the simulation and post-synthesis behavior are not the same!

通常，您不想使用电平敏感的锁存器.它们会引起各种麻烦，并且比普通的旧同步逻辑更难以验证.

Usually, you don't want to use level sensitive latches. They cause all sorts of trouble and they are harder to verify than plain old synchronous logic.

如果您真的想创建一个电平敏感的锁存器，则应该实例化FPGA供应商提供的锁存器，或者弄清楚使用哪种编码风格来使综合工具推断出锁存器

If you really want to create an level sensitive latch, you should either instantiate one that is provided by your FPGA vendor, or figure out which coding style to use to make your synthesis tool infer a latch.

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