在多核处理器中，如何找到最慢的内核的仿真时间? [英] In a multi-core processor, how can I find the simulation time of the slowest core?

问题描述

(对不起，如果我说错了这个问题)

(Sorry if I phrased the question incorrectly)

我正在16核Parallella板上运行一些应用程序，我想知道是否有一种方法可以计算最慢的核所花费的时间?

I am running some applications on a 16-core Parallella board and I was wondering if there was a way to calculate the amount of time taken by the slowest core?

我认为，如果我加上 user + sys 次，我将获得所有内核的执行时间总和，对吗?

I think that if I add the user + sys times, I will get the sum of the execution times for all the cores, correct?

以下是一些结果:

real        0m1.927s
user        0m3.190s
sys         0m0.080s

推荐答案

消歧

以并行"方式安排的基于多核的操作模式与并行模式处理之间存在很大差异.

Disambiguation

There is a strong difference between a multi-core based mode of operations, arranged in a "concurrent" manner and a parallel mode processing.

在Parallella板上，如果谈到Zynq –双核ARM Cortex-A9 CPU/Xilinx 7系列片上FPGA –为此，您可以获得 user 板载linux中的 sys 值.对于 Epiphany MPPA (大规模并行处理器阵列)硬件设备或其他可并行化的 FPGA -硬件可加载软CPU内核，是不相同的.

On Parallella board, if speaking about Zynq -- a dual-core ARM Cortex-A9 CPU / Xilinx 7-series on chip FPGA -- for that you can get user + sys values from on-board linux. Not the same for the Epiphany MPPA ( Massive Parallel Processor Array ) hardware device or additional parallelisable FPGA-hardware loadable soft-CPU-cores.

还要注意，在真正的并行系统上，慢"或最慢"内核一词在所有处理器以并行方式启动和结束时都失去了其含义，有关详细信息，请参见 PAR occam-pi 中的语法构造函数(甚至以等待不同的替代处理路径为代价，因为它们都并行完成).

Also note, that on a truly parallel system, the word "slower" or "slowest" core, loses its meaning as all processors start and finish in a parallel manner, for details kindly see the PAR syntax constructor in occam-pi ( even at a cost of waiting for a divergent alternative path of processing, so as they all finish in parallel ).

其中一个可能包含一些信令数据，以在MPPA代码执行期间存储时钟计数器值，随后再从Linux/ARM端检索该时钟计数器值，并使用这些遥测记录数据评估预先记录的代码执行时序.内部MPPA".

One may include some signalling data to store during MPPA code-execution a clock counter value / later retrieved from Linux/ARM-side and use these telemetry-records data to evaluate ex-post the code-execution timing pre-recorded "inside-MPPA".

对于体内跟踪/状态诊断/检查分析工具，可以实时进行相同的操作，但是对于这样的Real-Sys-SysMONITOR，则需要大量系统特定的工程工作.

Doing the same in-real-time might be possible for in-vivo Tracing / State-Diagnostics / Inspect-Analyse-Tool but would require a lot of system specific engineering efforts for such a Real-Time-SysMONITOR.

但这是可行的.在FSA设计/验证中，使用了类似的方法对状态转换进行视觉检查.

However this is doable. Similar approach was used for visual inspection of state-transitions in FSA-design / validation.

很好地解释了 PARALLEL ， SERIAL 和 CONCURRENT 的代码执行模式.

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