什么是ARM cortex m0/m0 +中的可中断重启指令 [英] what is Interruptible-restartable instructions in ARM cortex m0/m0+

问题描述

我目前正在阅读如下所示的ARM网站上的《 ARM Cortex M0 +用户指南》 http://infocenter.arm. com/help/index.jsp?topic =/com.arm.doc.dui0662b/CHDBIBGJ.html

I am currently reading ARM Cortex M0+ User Guide on ARM website shown below http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0662b/CHDBIBGJ.html

在用户手册中，提到了以下段落:

In User Manual, following paragraph is mentioned:

可中断重启指令
中断可重启指令是LDM，STM，PUSH，POP，在32周期乘法器实现中是MULS.当执行这些指令之一时发生中断时，处理器将放弃执行该指令.处理完中断后，处理器从头开始重新执行指令.

Interruptible-restartable instructions
The interruptible-restartable instructions are LDM, STM, PUSH, POP and, in 32-cycle multiplier implementations, MULS. When an interrupt occurs during the execution of one of these instructions, the processor abandons execution of the instruction. After servicing the interrupt, the processor restarts execution of the instruction from the beginning.

我无法理解可重启指令的工作原理?有人可以通过示例向我解释可中断可重启指令的不同阶段(获取，解码和执行)吗?中断到来时指令流水线会发生什么?

I am not able to understand how restartable instructions works? Can somebody explain me different phases (fetch, decode and execute) of Interruptible-restartable instructions with an example? what happens to instruction pipeline when interrupt comes?

推荐答案

对于LDM，执行阶段实际上是多个周期(每个寄存器至少一个周期).

For an LDM, the execute stage is actually multiple cycles (at least one for each register).

这是简单的提取/解码/执行模型开始崩溃的地方-execute实际上是一个非平凡的状态机，可以经常表示一个周期，但是有少数特殊"状态操作.

This is where the simple fetch/decode/execute model starts to break down - execute is actually a non-trivial state machine which can often represent a single cycle, but has a handful of 'special' operations.

使用Cortex M，即使在基本级别上，当发生异常时，除了将获取指向异常处理程序并等待执行脱离当前指令后等待执行释放之外，还有很多工作要做

With Cortex M, even at a basic level, when an exception occurs, there is a whole lot more work to do other than just pointing fetch at the exception handler and waiting for execute to become free after breaking out of its current instruction.

在硬件级别理解不间断和可重新启动指令的关键部分是它们由体系结构寄存器控制，并且没有很多中间状态.处于中间状态时，它将存储在EPSR.ICI中.还有一些中间寄存器存储区用于诸如乘法中间结果之类的事情，因此体系结构寄存器可以在不损坏的情况下进行恢复.

The key part to understanding both the uninterruptible and restartable instructions at a hardware level is that they are controlled by the architectural registers, and there is not a lot of intermediate state. Where there is intermediate state, it is stored in EPSR.ICI. There is also some intermediate register storage used for things like multiplication intermediate results so the architectural registers can be recovered without corruption.

关于为什么的架构致力于支持可重新启动或可持续的指令(如注释中所述)，这专门用于改善中断等待时间(这是Cortex-M的关键之一)特征).对于单个加载或存储，程序员通常具有足够的控制权，可以在中断延迟至关重要的情况下避免风险太长的数据接口停顿，并且对12个周期的延迟不应有太大影响.对于多个加载/存储，延迟可能会很大(从程序的角度来看，当异常悬而未决时，像堆栈压入之类的操作就毫无价值，因为处理程序本身会满足即时的上下文保存要求).由于这些处理器通常仅具有一个数据存储器接口，因此微代码异常堆栈无法与完成加载/存储倍数的其余拍子并行进行.

As to why the architecture goes to the effort of supporting restartable or continuable instructions (as mentioned in the comments), this is specifically to improve interrupt latency (which is one of the key Cortex-M features). For a single load or store, the programmer generally has enough control over not risking too long a data interface stall when interrupt latency is critical, and there should not be too much impact on the 12 cycle latency. For a load/store multiple, the delay can be significant (and from a program point of view, something like a stack push is of no value when an exception is pending since the handler will itself take care of the immediate context save requirements). Since these processors typically only have a single data memory interface, the microcoded exception stacking can't take place in parallel with completing the remaining beats of a load/store multiple.

需要折衷选择多个循环指令，这些指令被简单地放弃，被暂停以在以后继续使用的指令，以及必须完成的指令.由于总线接口，一旦开始传输，它就必须完成.连续的指令不是原子的，并且可重新启动的指令可能导致重复访问同一地址(因此，在写入外围设备fifo等时必须避免这些操作).通过保持良好的中断性能，对于目标应用程序而言，所有这些额外的复杂性仍然是合理的，并且通常不需要程序员担心精确的细节.另一种选择是在各个地方使用单独的LDM，这从代码密度的角度来看效率低下(并且潜在性能取决于uArch/系统).

There is a trade off with multi-cycle instructions which are simply abandoned, instructions which are paused to continue later, and instructions which must complete. As a consequence of the bus interface, once a transfer has started, it must complete. Continuable instructions are not atomic, and restartable instructions can result in repeated accesses to the same address (so these must be avoided when writing to peripheral fifos and the like). All of this extra complication is still justified for the target application by maintaining good interrupt performance, and usually not requiring the programmer to worry about the precise details. The alternative would be to use individual LDM everywhere which is inefficient from a code density point of view (and potentially performance depending on the uArch/system).

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