ARM cortex m0/m0+ 中的可中断重启指令是什么 [英] what is Interruptible-restartable instructions in ARM cortex m0/m0+

问题描述

我目前正在 ARM 网站上阅读 ARM Cortex M0+ 用户指南，如下所示http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0662b/CHDBIBGJ.html

在用户手册中，提到了以下段落:

In User Manual, following paragraph is mentioned:

可中断重启指令
可中断-可重启指令是 LDM、STM、PUSH、POP 以及在 32 周期乘法器实现中的 MULS.当在这些指令之一的执行过程中发生中断时，处理器放弃该指令的执行.服务中断后，处理器从头开始重新执行指令.

Interruptible-restartable instructions
The interruptible-restartable instructions are LDM, STM, PUSH, POP and, in 32-cycle multiplier implementations, MULS. When an interrupt occurs during the execution of one of these instructions, the processor abandons execution of the instruction. After servicing the interrupt, the processor restarts execution of the instruction from the beginning.

我无法理解可重启指令的工作原理?有人可以通过示例向我解释可中断可重启指令的不同阶段(获取、解码和执行)吗?中断来临时指令流水线会发生什么?

I am not able to understand how restartable instructions works? Can somebody explain me different phases (fetch, decode and execute) of Interruptible-restartable instructions with an example? what happens to instruction pipeline when interrupt comes?

推荐答案

对于 LDM，执行阶段实际上是多个周期(每个寄存器至少一个).

For an LDM, the execute stage is actually multiple cycles (at least one for each register).

这是简单的获取/解码/执行模型开始崩溃的地方 - 执行实际上是一个非平凡的状态机，它可以经常表示单个周期，但有一些特殊"' 操作.

This is where the simple fetch/decode/execute model starts to break down - execute is actually a non-trivial state machine which can often represent a single cycle, but has a handful of 'special' operations.

使用 Cortex M，即使在基本级别，当异常发生时，除了将 fetch 指向异常处理程序并等待 execute 在中断当前指令后变为空闲之外，还有很多工作要做.

With Cortex M, even at a basic level, when an exception occurs, there is a whole lot more work to do other than just pointing fetch at the exception handler and waiting for execute to become free after breaking out of its current instruction.

在硬件层面理解不可中断和可重启指令的关键部分是它们由架构寄存器控制，并且没有很多中间状态.在有中间状态的地方，它存储在 EPSR.ICI 中.还有一些中间寄存器存储用于诸如乘法中间结果之类的事情，因此可以在不损坏的情况下恢复架构寄存器.

The key part to understanding both the uninterruptible and restartable instructions at a hardware level is that they are controlled by the architectural registers, and there is not a lot of intermediate state. Where there is intermediate state, it is stored in EPSR.ICI. There is also some intermediate register storage used for things like multiplication intermediate results so the architectural registers can be recovered without corruption.

至于为什么架构致力于支持可重启或可继续指令(如评论中所述)，这是专门为了改善中断延迟(这是 Cortex-M 的关键之一特征).对于单个加载或存储，当中断延迟很关键时，程序员通常有足够的控制权，不会冒数据接口停顿时间过长的风险，也不应对 12 周期延迟有太大影响.对于加载/存储多个，延迟可能很重要(并且从程序的角度来看，当异常未决时，堆栈推送之类的东西没有价值，因为处理程序本身会处理即时上下文保存要求).由于这些处理器通常只有一个数据存储器接口，因此微编码异常堆栈不能与完成加载/存储多个剩余节拍并行发生.

As to why the architecture goes to the effort of supporting restartable or continuable instructions (as mentioned in the comments), this is specifically to improve interrupt latency (which is one of the key Cortex-M features). For a single load or store, the programmer generally has enough control over not risking too long a data interface stall when interrupt latency is critical, and there should not be too much impact on the 12 cycle latency. For a load/store multiple, the delay can be significant (and from a program point of view, something like a stack push is of no value when an exception is pending since the handler will itself take care of the immediate context save requirements). Since these processors typically only have a single data memory interface, the microcoded exception stacking can't take place in parallel with completing the remaining beats of a load/store multiple.

简单地放弃的多周期指令、暂停以稍后继续的指令以及必须完成的指令之间存在折衷.作为总线接口的结果，一旦传输开始，它必须完成.可连续指令不是原子的，可重启指令会导致对同一地址的重复访问(因此在写入外围 fifo 等时必须避免这些).通过保持良好的中断性能，所有这些额外的复杂性对于目标应用程序来说仍然是合理的，并且通常不需要程序员担心精确的细节.另一种方法是在任何地方使用单独的 LDM，从代码密度的角度来看这是低效的(并且潜在的性能取决于 uArch/系统).

There is a trade off with multi-cycle instructions which are simply abandoned, instructions which are paused to continue later, and instructions which must complete. As a consequence of the bus interface, once a transfer has started, it must complete. Continuable instructions are not atomic, and restartable instructions can result in repeated accesses to the same address (so these must be avoided when writing to peripheral fifos and the like). All of this extra complication is still justified for the target application by maintaining good interrupt performance, and usually not requiring the programmer to worry about the precise details. The alternative would be to use individual LDM everywhere which is inefficient from a code density point of view (and potentially performance depending on the uArch/system).

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