怎么样！ LDM R1的一部分！ {R2}" Armv6-M架构中的指令已编码? [英] How is "!" part of "LDM R1! {R2}" instruction in Armv6-M Architecture Encoded?

问题描述

当我查看Arm的官方规格时，

When I look at the official Arm specifications,

! 
Causes the instruction to write a modified value back to <Rn> . If ! is omitted, the instruction does not change <Rn> in this way.

这是功能的解释方式，但ASL代码如下，

This is how the function is explained, yet the ASL Code is as follows,

if ConditionPassed() then
  n = UInt(Rn); registers = '00000000':register_list;
  if BitCount(registers) < 1 then UNPREDICTABLE;
  wback = (registers<n> == '0');
  address = R[n];
  for i = 0 to 7
    if registers<i> == '1' then
      R[i] = MemA[address,4];
      address = address + 4;
if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);

因此，唯一合乎逻辑的事情是使用wback来实现此目的，但是当我检查通用结构时似乎并没有加起来.

So the only logical thing would be to use wback for the purpose, yet it doesn't seem to add up when I examine the general structure.

推荐答案

在arm文档中对其进行了记录.

It is documented in the arm documentation.

如果您习惯使用w位，一开始看起来很奇怪，因此可能会导致您检查armv7-m，armv7-ar，因此当然要回到原始的手臂上

Initially it looks strange if you are used to the w bit and so that might lead you to check the armv7-m, armv7-ar, so of course go back to the original arm arm

! Causes base register writeback, and is not optional.

您也可以尝试一下，看看汇编程序对此有何看法

You can also try it and see what an assembler thinks of it

.cpu cortex-m0
.thumb
ldm r1,{r2}
ldm r1!,{r2}

arm-none-eabi-as so.s -o so.o
so.s: Assembler messages:
so.s:4: Warning: this instruction will write back the base register

第4行是没有！

Disassembly of section .text:

00000000 <.text>:
   0:   c904        ldmia   r1!, {r2}
   2:   c904        ldmia   r1!, {r2}

经进一步检查，这不是文档中的错误

Upon further inspection it is not a bug in the documentation though

LDM <Rn>,<registers> <Rn> included in <registers>

所以测试一下

.cpu cortex-m0
.thumb
ldm r1,{r1}
ldm r1!,{r1}
so.s: Assembler messages:
so.s:5: Warning: this instruction will not write back the base register

第5行是带有！

Disassembly of section .text:

00000000 <.text>:
   0:   c902        ldmia   r1, {r1}
   2:   c902        ldmia   r1, {r1}

arm文档中的psuedocode中也说明了以下内容:

Which is also stated in the psuedocode from the arm documentation:

if wback && registers<n> == ‘0’ then R[n] = R[n] + 4*BitCount(registers);

因此，它不像较大的指令中那样被编码为比特，这是基于寄存器列表中存在rn所隐含的.

so this is not encoded as a bit as in the larger instructions, this is implied based on the presence of rn in the register list.

现在回到原来的手臂上

Operand restrictions
If the base register <Rn> is specified in <registers>, the final value of <Rn> is the loaded value (not the written-back value).

因此即使是原始文件也不会被回写.如果您进行测试，gnu汇编程序也会通过类似的消息知道这一点

so even in the original it is not written back. and if you test it gnu assembler knows this as well with similar messages

.cpu arm7tdmi
.thumb
ldm r1,{r1}
ldm r1!,{r1}


arm-none-eabi-as so.s -o so.o
so.s: Assembler messages:
so.s:5: Warning: this instruction will not write back the base register

Disassembly of section .text:

00000000 <.text>:
   0:   c902        ldmia   r1, {r1}
   2:   c902        ldmia   r1, {r1}

这可能是armv4天内的故意事情，因为他们正试图作为一家知识产权公司和许多不可预测的结果来运营，而其他类似的事情实际上是可以预测的，并且它们是如何测试以查看您是否偷了核.如果以原始的arm docs编写的方式也能抓住那些制作克隆的人，这不会令我感到惊讶.

This is perhaps an intentional thing in the armv4 days as they were trying to operate as an IP company and a number of the UNPREDICTABLE RESULTS, and other such things were actually predictable and were how they tested to see if you had stolen a core. It would not surprise me if the way this was written in the original arm arm docs was also something to catch folks making clones.

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