ARM中断和上下文保存 [英] ARM interrupts and context saving

问题描述

我试图了解中断在ARM体系结构(具体来说是ARM7TDMI)中如何工作.我知道有七个异常(重置，数据中止，FIQ，IRQ，预取中止，SWI和未定义指令)，它们以特定的模式执行(分别是Supervisor，Abort，FIQ，IRQ，Abort，Supervisor和Undefined).我有以下问题.

1.当CPSR(状态寄存器)中的I和F位设置为1以禁用外部中断和快速中断时，是否也禁用了其他5个异常? 2.如果在启用I和F位时未禁用SWI，那么是否有可能在外部中断的ISR内故意触发SWI异常? 3.当触发任何中断以将CPSR保存为SPSR时，更改模式由处理器本身完成.因此，编写ISR处理程序函数并用处理程序地址更新向量表是否足够(我不想将r0保存到r12通用寄存器)?

4.每当更改执行方式时，处理器是否会在内部进行上下文保存(即使我们手动更改方式)?

5.如何屏蔽/禁用SWI异常?


谢谢.

I am trying to understand how interrupts work in an ARM architecture(ARM7TDMI to be specific). I know that there are seven exceptions (Reset,Data Abort, FIQ, IRQ, Pre-fetch abort, SWI and Undefined instruction) and they execute in particular modes(Supervisor, Abort, FIQ, IRQ, Abort, Supervisor and Undefined respectively). I have the following questions.

1. When the I and F bits in CPSR(status register) are set to 1 to disable external and fast interrupt, does the other 5 exceptions are also disabled ?

2. If the SWI is not disabled when I and F bits are enabled then, is it possible to intentionally trigger a SWI exception within ISR of an external interrupt?

3.When any interrupt is triggered saving the CPSR to SPSR, changing the mode is done by the processor itself. So, is it enough to write the ISR handler function and update the vector table with the handler addresses(I don't want to save r0 to r12 general purpose registers) ?

4. Whenever the mode of execution is changed does context saving happens internally by the processor(even when we change the mode manually)?

5. How to mask/disable a SWI exception?


Thank you.

推荐答案

1. 当CPSR(状态寄存器)中的I和F位设置为1以禁用外部中断和快速中断时，其他5个异常是 还禁用了吗?

1. When the I and F bits in CPSR(status register) are set to 1 to disable external and fast interrupt, does the other 5 exceptions are also disabled ?

否，所有这些都取决于您的代码是否正确.例如，编译器通常不会生成swi指令.

No, these all depend on your code to be correct. For instance, a compiler will not normally generate an swi instruction.

1. 如果在启用I和F位时未禁用SWI，则有可能在ISR的ISR内有意触发SWI异常 外部中断?

1. If the SWI is not disabled when I and F bits are enabled then, is it possible to intentionally trigger a SWI exception within ISR of an external interrupt?

是的，有可能.您可以在swi处理程序中检查 SPSR 的模式，并根据需要中止(或任何适当的操作).

Yes, it is possible. You may check the mode of the SPSR in your swi handler and abort (or whatever is appropriate) if you want.

3.当触发任何中断以将CPSR保存为SPSR时，更改模式由处理器本身完成.所以，写就够了吗 ISR处理程序功能，并使用该处理程序更新向量表 地址(我不想将r0保存到r12通用寄存器)?

3.When any interrupt is triggered saving the CPSR to SPSR, changing the mode is done by the processor itself. So, is it enough to write the ISR handler function and update the vector table with the handler addresses(I don't want to save r0 to r12 general purpose registers) ?

没有人想要保存寄存器.但是，如果使用r0到r12，则主代码将损坏.存储区sp用于存储这些寄存器.而且，向量表不是处理程序地址，而是指令/代码.

No one wants to save registers. However, if you use r0 to r12 then the main code will become corrupt. The banked sp is made to store these registers. Also, the vector table is not a handler address but an instruction/code.

1. 只要更改执行模式，处理器都会在内部进行上下文保存(即使我们更改了模式， 手动)?

1. Whenever the mode of execution is changed does context saving happens internally by the processor(even when we change the mode manually)?

否，向量页面中的指令/代码负责保存上下文.如果您具有可抢占式操作系统，则需要保存该过程的上下文并稍后还原.您可能有数千个进程.因此，CPU无法自动执行此操作.您的上下文保存区域可能植根于super mode堆栈；在这种情况下，您可以将ISR/FIQ sp用作临时寄存器.例如， thread_info 植根于超级用户堆栈中，用于用户空间进程/线程的内核管理.最小代码(已删除功能)为

No, the instruction/code in the vector page is responsible for saving the context. If you have a pre-emptable OS then you need to save the context for the process and restore later. You may have 1000s of processes. So a CPU could not do this automatically. Your context save area may be rooted in the super mode stack; you can use the ISR/FIQ sp as a temporary register in this case. For instance, the switch_to function in ARM Linux maybe helpful. thread_info is rooted in the supervisor stack for the kernel management of the user space process/thread. The minimum code (with features removed) is,

__switch_to:
    add ip, r1, #TI_CPU_SAVE                @ Get save area to `ip`.
    stmia   ip!, {r4 - sl, fp, sp, lr} )    @ Store most regs on stack
    add r4, r2, #TI_CPU_SAVE                @ Get restore area to `r4`
    ldmia   r4, {r4 - sl, fp, sp, pc}  )    @ Load all regs saved previously
    @ note the last instruction returns to a previous 
    @ switch_to call by the destination thread/process

1. 如何屏蔽/禁用SWI异常?

您不能这样做.您可以编写一个swi处理程序，该处理程序除了增加PC之外什么都不做，和/或您可以根据其作用跳到 undefined 处理程序.

You can not do this. You could write an swi handler that does nothing but increment the PC and/or you could just jump to the undefined handler depending on what it does.

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