ARM 中断和上下文保存 [英] ARM interrupts and context saving

问题描述

我试图了解中断在 ARM 架构(具体来说是 ARM7TDMI)中是如何工作的.我知道有七种异常(复位、数据中止、FIQ、IRQ、预取中止、SWI 和未定义指令)并且它们在特定模式下执行(分别为 Supervisor、Abort、FIQ、IRQ、Abort、Supervisor 和 Undefined).我有以下问题.

1. 当CPSR(状态寄存器)中的I和F位设置为1以禁用外部和快速中断时，其他5个异常是否也被禁用?

2.如果在I和F位使能时SWI没有被禁止，那么是否可以在外部中断的ISR内故意触发SWI异常?

3.当触发任何中断将CPSR保存到SPSR时，改变模式由处理器自己完成.那么，编写 ISR 处理程序函数并使用处理程序地址更新向量表是否足够(我不想将 r0 保存到 r12 通用寄存器)?

4. 每当执行模式改变时，处理器是否会在内部进行上下文保存(即使我们手动改变模式)?

5. 如何屏蔽/禁用 SWI 异常?


谢谢.

解决方案

1. 当CPSR(状态寄存器)中的I和F位设置为1以禁用外部和快速中断时，其他5个异常是否为也被禁用了?

不，这些都取决于您的代码是否正确.例如，编译器通常不会生成 swi 指令.

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2. 如果在启用 I 和 F 位时未禁用 SWI，那么是否有可能在 ISR 的 ISR 内有意触发 SWI 异常?外部中断?

是的，这是可能的.如果需要，您可以在 swi 处理程序中检查 SPSR 的模式并中止(或任何适当的).

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3.当触发任何中断将CPSR保存到SPSR时，更改模式由处理器自己完成.那么，写够了吗ISR 处理程序函数并使用处理程序更新向量表地址(我不想将 r0 保存到 r12 通用寄存器)?

没有人想保存寄存器.但是，如果您使用 r0 到 r12，那么主代码将被破坏.存储的 sp 用于存储这些寄存器.此外，向量表不是处理程序地址，而是指令/代码.

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4. 每当执行模式改变时，处理器会在内部进行上下文保存(即使我们改变了模式手动)?

不，矢量页面中的指令/代码负责保存上下文.如果您有一个可抢占的操作系统，那么您需要保存进程的上下文并稍后恢复.您可能有 1000 个进程.因此 CPU 无法自动执行此操作.您的上下文保存区域可能根植于 super mode 堆栈中；在这种情况下，您可以使用 ISR/FIQ sp 作为临时寄存器.例如， switch_to ARM Linux 中的函数可能会有所帮助.thread_info 植根于监督者堆栈，用于用户空间进程/线程的内核管理.最小代码(删除功能)是，

__switch_to:添加 ip, r1, #TI_CPU_SAVE @ Get save area to `ip`.stmia ip!, {r4 - sl, fp, sp, lr} ) @ 将大多数 regs 存储在堆栈中添加 r4, r2, #TI_CPU_SAVE @ 获取恢复区域到 `r4`ldmia r4, {r4 - sl, fp, sp, pc} ) @ 加载之前保存的所有 regs@注意最后一条指令返回到前一条@switch_to 由目标线程/进程调用

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5. 如何屏蔽/禁用 SWI 异常?

你不能这样做.您可以编写一个 swi 处理程序，它除了增加 PC 之外什么都不做，并且/或者您可以根据它的作用直接跳转到 undefined 处理程序.

I am trying to understand how interrupts work in an ARM architecture(ARM7TDMI to be specific). I know that there are seven exceptions (Reset,Data Abort, FIQ, IRQ, Pre-fetch abort, SWI and Undefined instruction) and they execute in particular modes(Supervisor, Abort, FIQ, IRQ, Abort, Supervisor and Undefined respectively). I have the following questions.

1. When the I and F bits in CPSR(status register) are set to 1 to disable external and fast interrupt, does the other 5 exceptions are also disabled ?

2. If the SWI is not disabled when I and F bits are enabled then, is it possible to intentionally trigger a SWI exception within ISR of an external interrupt?

3.When any interrupt is triggered saving the CPSR to SPSR, changing the mode is done by the processor itself. So, is it enough to write the ISR handler function and update the vector table with the handler addresses(I don't want to save r0 to r12 general purpose registers) ?

4. Whenever the mode of execution is changed does context saving happens internally by the processor(even when we change the mode manually)?

5. How to mask/disable a SWI exception?


Thank you.

解决方案

1. When the I and F bits in CPSR(status register) are set to 1 to disable external and fast interrupt, does the other 5 exceptions are also disabled ?

No, these all depend on your code to be correct. For instance, a compiler will not normally generate an swi instruction.

2. If the SWI is not disabled when I and F bits are enabled then, is it possible to intentionally trigger a SWI exception within ISR of an external interrupt?

Yes, it is possible. You may check the mode of the SPSR in your swi handler and abort (or whatever is appropriate) if you want.

3.When any interrupt is triggered saving the CPSR to SPSR, changing the mode is done by the processor itself. So, is it enough to write the ISR handler function and update the vector table with the handler addresses(I don't want to save r0 to r12 general purpose registers) ?

No one wants to save registers. However, if you use r0 to r12 then the main code will become corrupt. The banked sp is made to store these registers. Also, the vector table is not a handler address but an instruction/code.

4. Whenever the mode of execution is changed does context saving happens internally by the processor(even when we change the mode manually)?

No, the instruction/code in the vector page is responsible for saving the context. If you have a pre-emptable OS then you need to save the context for the process and restore later. You may have 1000s of processes. So a CPU could not do this automatically. Your context save area may be rooted in the super mode stack; you can use the ISR/FIQ sp as a temporary register in this case. For instance, the switch_to function in ARM Linux maybe helpful. thread_info is rooted in the supervisor stack for the kernel management of the user space process/thread. The minimum code (with features removed) is,

__switch_to:
    add ip, r1, #TI_CPU_SAVE                @ Get save area to `ip`.
    stmia   ip!, {r4 - sl, fp, sp, lr} )    @ Store most regs on stack
    add r4, r2, #TI_CPU_SAVE                @ Get restore area to `r4`
    ldmia   r4, {r4 - sl, fp, sp, pc}  )    @ Load all regs saved previously
    @ note the last instruction returns to a previous 
    @ switch_to call by the destination thread/process

5. How to mask/disable a SWI exception?

You can not do this. You could write an swi handler that does nothing but increment the PC and/or you could just jump to the undefined handler depending on what it does.

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