为什么在x86-64中，虚拟地址比物理地址短4位(48位与52位长)? [英] Why in x86-64 the virtual address are 4 bits shorter than physical (48 bits vs. 52 long)?

问题描述

在底层编程:英特尔®64架构上的C，汇编和程序执行"一书中，我读到:

In the book "Low-Level Programming: C, Assembly, and Program Execution on Intel® 64 Architecture" I read:

每个虚拟64位地址(例如，我们在程序中使用的地址) 由几个领域组成.地址本身实际上只有48位 宽的;它被符号扩展到64位规范地址.它的 特点是它的17个左位相等.如果条件是 如果不满意，该地址将在使用后立即被拒绝.然后 48位虚拟地址转换为52位物理地址 在特殊表的帮助下进行地址处理.

Each virtual 64-bit address (e.g., ones we are using in our programs) consists of several fields. The address itself is in fact only 48 bits wide; it is sign-extended to a 64-bit canonical address. Its characteristic is that its 17 left bits are equal. If the condition is not satisfied, the address gets rejected immediately when used. Then 48 bits of virtual address are transformed into 52 bits of physical address with the help of special tables.

为什么虚拟地址和物理地址在4位上有区别?

Why is the difference in 4 bits between the virtual address and the physical address?

推荐答案

我相信您在谈论x86-64，我的回答是基于该架构的.

I believe you are talking about x86-64, my answer is based on that architecture.

以64位模式运行时，CPU使用经过改进的功能将虚拟地址转换为称为 PAE-物理地址扩展名.
最初是为了打破4GiB限制而仍然使用32位指针而发明的，此功能涉及使用4级表.
每个表都提供了指向下一个表的指针，该指针一直指向最右边的一个指针，该指针给出了物理地址的高位.要了解一个想法，请参见 AMD64体系结构编程手册:

When operating in 64-bit mode the CPU uses a revamped feature to translate virtual addresses into physical addresses known as PAE - Physical address extension.
Originally invented to break the 4GiB limit while still using 32-bit pointers, this feature involves the use of 4 level of tables.
Each table gives a pointer to the next table, down to the rightmost one that gives the upper bits of physical address. To get an idea look at this picture from the AMD64 Architecture Programming Manual:

所有这些表的基本原理是 sparsity :将虚拟地址转换为物理地址的元数据非常大-如果我们仅使用4KiB页面，则需要2 ^64-12 = 2 ⁵² 项，以覆盖整个64位地址空间.
表允许使用稀疏方法，只有必要的条目才会填充到内存中.

The rationale behind all those tables is sparsity: the metadata for translating virtual addresses into physical addresses is huge - if we were to use 4KiB pages only we'd need 2^{64 - 12} = 2⁵² entries to cover the whole 64-bit address space.
Tables allow for a sparse approach, only the entries necessary are populated in memory.

这种设计反映在虚拟地址的划分方式上(因此间接地在级别数上)，仅使用9位游程对每个级别的表进行索引.
从包括的第12位开始，它给出了:级别1-> 12-20，级别2-> 21-29，级别3-> 30-38，级别4-> 39-47.

This design is reflected in how the virtual address is divided (and thus, indirectly, in the number of levels), only runs of 9 bits are used to index the tables at each level.
Starting from bit 12 included, this gives: level 1 -> 12-20, level 2 -> 21-29, level 3 -> 30-38, level 4 -> 39-47.

这说明了目前仅48位虚拟地址空间的实现限制.
请注意，在使用逻辑地址的指令级别，我们完全支持64位地址.
分段级别也提供了全面支持，该部分将逻辑地址转换为线性地址.
因此，限制来自PAE.

This explains the current implementation limit of only 48 bits of virtual address space.
Note that at the instruction level, where logical addresses are used, we have full support for 64 bits addresses.
Full support is also available at the segmentation level, the part that translates logical addresses into linear addresses.
So the limitation comes from PAE.

我的个人观点是AMD急于成为第一个发布具有64位支持和重用PAE的x86 CPU的公司，并对其进行了修补，以新的间接级别对其进行了翻译，以转换多达48位.
请注意，Intel和AMD都允许将来的实现将64位用于虚拟地址(可能带有更多表).

My personal opinion is that AMD rushed to be the first to ship an x86 CPU with 64-bit support and reused PAE, patching it with a new level of indirection to translate up to 48 bits.
Note that both Intel and AMD allow a future implementation to use 64 bits for the virtual address (probably with more tables).

但是，两家公司都将物理地址的硬限制设置为52位. 为什么?

However, both companies set a hard limit of 52 bit for the physical address. Why?

仍然可以在分页的工作方式中找到答案.
在32位模式下，每个表中的每个条目均为32位宽；低位用作标志(因为对齐要求使它们在翻译过程中无用)，但高位全部用于翻译，从而提供了32/32的虚拟/物理翻译.
需要强调的是，所有32位都已使用，而某些低位未用作标志，英特尔将其标记为已忽略"或可用"，这意味着操作系统可以自由使用它们.

The answer can still be found in how paging work.
In 32-bit mode, each entry in each table is 32 bits wide; the low bits are used as flags (since the alignment requirements make them useless for the translation process) but the higher bits were all used for the translation, giving a 32/32 virtual/physical translation.
It's important to stress out that all the 32 bits were used, while some of the lower bits were not used as flags, Intel marked them as "Ignored" or "Available" meaning with that that the OS was free to use them.

当英特尔推出PAE时，他们需要再增加4位(那时PAE为36位)，因此逻辑上要做的是将每个条目的大小 加倍，因为这样可以创建比布局更有效的布局一个40位表条目.
这给了Intel大量的可用空间，他们将其标记为已保留(在旧版本的Intel SDM手册

When Intel introduced PAE, they needed 4 more bits (PAE was 36 bits back then) and the logical thing to do was to double the size of each entry since this creates a more efficient layout than a, say, 40-bit table entry.
This gave Intel a lot of spare space and they marked it as reserved (This can be better observed in older versions of the Intel SDM manuals, like this one).

随着时间的流逝，条目中需要新的属性，其中最著名的是 XD/NX位.
保护锁也是一项相对较新的功能，它占用条目中的空间. 这表明当前的ISA无法再进行完整的64/64位虚拟/物理转换.

With time, new attributes were needed in an entry, the most famous one being the XD/NX bit.
Protection keys are also a, relatively new, feature that takes space in an entry. This shows that a full 64/64 bits virtual/physical translation is not possible anymore with the current ISA.

为便于参考，以下是64位PAE表条目的格式:

For a visual reference, here is the format of the 64-bit PAE table entries:

它表明不可能使用64位物理地址(对于大页面，仍然可以解决此问题，但考虑到位的布局似乎不太可能)，但无法解释为什么AMD将限制设置为52位.

It shows that a 64-bit physical address is not possible (for huge pages there still is a way to fix this but given the layout of the bits that seems unlikely) but doesn't explain why AMD set the limit to 52 bits.

好吧，很难说.
当然，物理地址空间的大小会带来一些 hardware 成本:更多的引脚(尽管集成了内存控制器，但由于DDR规范多路复用了许多信号，这种情况得以缓解)在缓存/TLB中.
在此问题(类似，但不足以使其重复)答案城市维基百科，据称引用了AMD，声称AMD的工程师在考虑了收益和成本后将限制设置为52位.

Well, it's hard to say.
Certainly, the size of the physical address space has some hardware cost associated with it: more pins (though with the integrated memory controller, this is mitigated as the DDR specs multiplex a lot of signals) and more space in the caches/TLBs.
In this question (similar but not enough make this a duplicate) an answer cities Wikipedia, that in turn allegedly cites AMD, claiming that AMD's engineers set the limit to 52 bits after due considerations of benefits and costs.

我分享了汉斯·帕桑(Hans Passant)于6年前写过文章:当前的分页机制不适用于完整的64位物理寻址，这可能是英特尔和AMD都从不保留每个条目的高位的原因.

I share what Hans Passant wrote more than 6 years ago: the current paging mechanisms are not suitable for a full 64-bit physical addressing and that's probably the reason why both Intel and AMD never bothered keeping the high bits in each entry reserved.

两家公司都知道，随着这项技术将达到52位的限制，它也将与实际形式大不相同.
到那时，他们将为总体上设计一种更好的内存机制，从而避免过度设计现有的内存机制.

Both companies know that as the technology will approach the 52-bit limit it will also be very different from its actual form.
By the time they will have designed a better mechanism for memory in general, so they avoided over-engineering the existing one.

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