在x86软件中断期间，究竟何时进行上下文切换? [英] During an x86 software interrupt, when exactly is a context switch made?
问题描述
我之所以这样问，是因为我试图在玩具内核中实现中断.因此，我知道发生中断时，CPU会将各种信息位压入堆栈.但是，我在网上进行搜索的每个地方都会以不同的顺序显示不同的信息.我也知道，如果中断发生在用户模式(Ring 3)中，则CPU必须先切换到内核模式(Ring 0)，然后才能执行ISR.我认为这与TSS和ss和esp有关，但是我不确定.我已经在互联网上阅读了各种不同的解释，但尚未在其中找到任何统一之处.
I am asking this because I am trying to implement interrupts in my toy kernel. So, I know that when an interrupt occurs, the CPU pushes various bits of information onto the stack. However, everywhere I search online shows different information in different order being pushed. I also know that if the interrupt occurred in user mode (Ring 3), the CPU must switch to kernel mode (Ring 0) before it can execute the ISR. I think it has something to do with the TSS and ss and esp, however I am not sure. I have read various different explanations all over the internet and have not found any uniformity in any of them yet.
所以，我的问题是，在中断期间(x86)CPU将数据按什么确切顺序推入堆栈，何时执行?在某个时间点上是否通过TSS进行了上下文切换，这是否会影响被压入堆栈的数据(如果有的话)?
So my question is, in what exact order does the (x86) CPU push data onto the stack during an interrupt and when does it do it, and at what point in time does it make a context switch via the TSS and how does this affect the data that is pushed onto the stack, if at all?
到目前为止，我从研究中学到了什么(如果错了，请纠正我):我很确定处理器会将eflags，cs和eip压入堆栈error code如有必要，请在中断期间执行.但是，这是所有推动的事情吗?我在其他地方读过ss和esp被推送，但是我不知道是否一直在发生，或者为什么被推送.
What I have learned from research so far (correct me if wrong): I am pretty sure the processor pushes eflags, cs and eip onto the stack as well as an error code if necessary during an interrupt. However, is this all that is pushed? I have read elsewhere that ss and esp are pushed but I don't know if this happens all the time, or why it is pushed.
此外，我相信CPU会在TSS中查找Ring0 ss和esp，并在某些时候 加载它们，但是我不确定何时加载.也许是在中断发生后立即执行此操作?另外，在所有这些过程中如何处理cs和ds? CPU是否从IDT中的条目加载了cs?那ds呢?我必须手动加载吗?
Furthermore, I believe that the CPU will look in the TSS for the Ring0 ss and esp and at some point load them, but I am not sure when. Perhaps it does this right after the interrupt occurs? Also, how is cs and ds handled during all of this? Is cs loaded by the CPU from the entry in the IDT? What about ds? Must I load that manually?
很抱歉，如果问错地方了，我不确定我还应该在哪里.
Sorry if this is the wrong place to ask, I am not sure where else I should.
