英特尔®事务同步扩展新指令(TSX-NI)与英特尔TSX有区别吗? [英] Is Intel® Transactional Synchronization Extensions New Instruction (TSX-NI) difference from Intel TSX?

问题描述

我在Intel的页面上找到

I found on Intel's page

https://ark.intel.com/products/97123/Intel-Core-i5-7500-Processor-6M-Cache-up-to-3_80-GHz

该处理器支持TSX-NI技术，但我在Google上找不到有关它的任何信息.是否与Intel TSX相同?如果有区别，那么我该如何使用它.

that this processor support TSX-NI technology but I can't find any information about it on google. Is it the same as Intel TSX. If it is difference, then how I can use it.

对不起，我的英语不好！ :)

Sorry for my bad English! :)

推荐答案

似乎只是一种营销手段.

It seems just a marketing embellishment.

我在Internet上，Intel手册或Intel ISA扩展手册中都没有找到对"TSX-NI"的引用.

I found no references to "TSX-NI" nor on the Internet nor in the Intel manuals nor in the Intel ISA extensions manual.

引用Intel ^{[ 1 ]}

Quoting Intel ^[1]

英特尔事务同步扩展(Intel TSX)有两种形式:HLE和RTM.

Intel Transactional Synchronization Extensions (Intel TSX) comes in two flavours: HLE and RTM.

由于其实现，这两个方面是分离的(可以彼此独立地支持)，并且只有RTM引入了新的指令.
因此，他们可能指的是RTM.

Due to their implementation, these two aspects are decoupled (either can be supported separately from the other) and only RTM introduces new instructions.
So they are probably referring to RTM.

我相信HLE是首先引入的，应该有支持HLE但不支持RTM的处理器(相反，虽然可能，但似乎不太现实).

I believe HLE was introduced first and there should be processors that support HLE but not RTM (the converse, while possible, seems implausible).

所以，也许这只是市场上正确的说法:此CPU支持我们最新的TSX功能！".

So, maybe, it is just the marketing correct way of saying: "This CPU supports our latest TSX features!".

作为参考，我在假定"TSX-NI"指的是"TSX RTM"的前提下，简要介绍了英特尔TSX的两个部分.
可以在 Intel手册1-第15章中找到完整的参考.

For reference, I wrote a brief introduction to the two parts of Intel TSX on the assumption that "TSX-NI" refers to "TSX RTM".
A complete reference can be found on Intel Manual 1 - Chapter 15.

HLE(硬件锁定清除)部件向后兼容.
我们仍然可以使用 CPUID.07H.EBX.HLE [bit 4] 测试其可用性，但是它是通过更改指令的前缀repne/repe的语义来实现的.

The HLE (Hardware Lock Elision) part is backwards compatible.
We can still test its availability with CPUID.07H.EBX.HLE[bit 4] but it is implemented by changing the semantic of the prefixes repne/repe for the instructions.

此功能由两个新"前缀组成:xacquire和xrelease. 现在，CPU能够进入事务状态，其中每次读取都添加到事务的 read-set 中，而每次写入都添加到事务的 write-set 中并且不会执行到内存.
粒度是高速缓存行的大小.

This feature consists in two "new" prefixes: xacquire and xrelease. The CPU is now capable of entering a transactional state where every read is added to the read-set of the transaction and every write is added to the write-set of the transaction and it is not carried out to memory.
The granularity is the size of a cache line.

如果线程从另一个线程的读取集读取或写入读取集或写入集，则事务将中止.
CPU恢复事务开始时的架构状态，然后以非事务方式重新执行指令.
如果事务成功完成，则所有已写入的内存都将以原子方式完全提交.

If a thread reads from the read-set, or writes to either the read-set or the write-set, of another thread then the transaction is aborted.
The CPU restore the architectural state as it was at the beginning of the transaction and re-execute the instructions non-transactionally.
If the transaction complete successfully, all the written memory is committed atomically altogether.

事务由xacquire和xrelease分隔.
它们可以嵌套，但是深度(超过该值将中止该事务)和可以消除的不同锁的数量(超出CPU不会取消新的锁但不会中止该事务)有一个限制.
当嵌套事务中止时，CPU重新开始执行最外层事务.

Transactions are delimited by xacquire and xrelease.
They can nest but there is a limit on the depth (above which the transaction is aborted) and on the number of different locks that can be elided (exceeded that the CPU won't elide new locks but won't abort the transaction).
When a nested transaction is aborted, the CPU restarts executing the outermost transaction.

xacquire(操作码F2，与repne相同)用于获取锁(即写入锁)并标记事务开始的指令之前. 不不会将此读取添加到写入集中(否则，由于每个线程向锁写入数据，因此不会发生并发操作，这将立即中止任何后续事务).
而是将其添加到读取集.

xacquire (opcode F2, same as repne) is used in front of the instruction that would acquire a lock (i.e. write to the lock) and marks the beginning of a transaction.
This read is not added to the write-set (or no concurrency could happen as every thread writes to the lock and that would abort any subsequent transaction immediately).
It is added to the read-set instead.

xrelease(操作码F3)用于将释放锁并标记事务结束的指令之前.
xrelease必须与xacquire一起使用在同一锁上，以与它配对并完成交易.

xrelease (opcode F3) is used in front of the instruction that would release a lock and marks the ending of the transaction.
xrelease must be used on the same lock used with xacquire to pair with it and complete the transaction.

xacquire仅可与以​​下说明的lock d版本一起使用:ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, XCHG.
xrelease具有相同的说明，加上MOV mem, reg和MOV mem, imm，但没有lock前缀.

xacquire can only be used with the lockd version of these instructions: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, XCHG.
xrelease with the same instructions plus MOV mem, reg and MOV mem, imm without a lock prefix.

如果存在HLE(或RTM)，则新指令xtest可用，它设置 ZF 是处理器在事务中是否为 not .

A new instruction xtest is available if HLE (or RTM) is present, it sets the ZF is the processor is not inside a transaction.

RTM(受限事务存储)不向后兼容.
可以使用 CPUID.07H.EBX.RTM [bit 11] 进行测试.

The RTM (Restricted Transactional Memory) is not backwards compatible.
It can be tested with CPUID.07H.EBX.RTM [bit 11].

它引入了三个新指令:xbegin，xend和xabort.
它们只是已指定的通用事务执行功能的新接口.

It introduces three new instructions: xbegin, xend and xabort.
They are just a new interface to the already specified, and common, transactional execution capability.

xbegin必须提供一个指向后备代码路径的指针作为相对偏移量. 每当事务提交失败时，就会执行此代码.
在这种情况下，eax保留了中止的原因. xend结束事务并指示CPU提交它.
xabort允许程序员使用自定义错误代码显式中止事务.

The xbegin must provide, as a relative offset, a pointer to the fallback code path.
This code is executed whenever the transaction fails to be committed.
In such cases eax holds the reason of the abort.
xend ends the transaction and instructs the CPU to commit it.
xabort lets the programmer abort the transaction explicitly with a custom error code.

英特尔不保证处理器成功提交事务的能力.
尽管HLE具有一组非常特定的条件，但是RTM是一种尽力而为"的功能-因此需要备用代码.

Intel makes no guarantees about the ability of the processor to successfully commit a transaction.
While HLE has a set of very specific conditions, RTM is a "best effort" kind of feature - thus the requirement for a fallback code.

RTM比HLE更底层，它使程序员可以在不使用锁的情况下使用事务性内存.

RTM is more low-level than HLE, it lets the programmer use transactional memory, with or without the use of locks.

引用Intel:

HLE和RTM嵌套在一起时的行为-HLE RTM内部或HLE内部的RTM是特定于实现的.但是，在所有情况下， 实现将保持HLE和RTM语义.一个实现可以 选择在RTM区域内使用时忽略HLE提示，并且在HLE区域内使用RTM指令时可能导致事务中止.在后一种情况下， 从事务执行到非事务执行的过渡是无缝发生的 因为处理器将在不实际执行省略的情况下重新执行HLE区域，并且 然后执行RTM指令.

The behaviour when HLE and RTM are nested together—HLE inside RTM or RTM inside HLE—is implementation specific. However, in all cases, the implementation will maintain HLE and RTM semantics. An implementation may choose to ignore HLE hints when used inside RTM regions, and may cause a transactional abort when RTM instructions are used inside HLE regions. In the latter case, the transition from transactional to non-transactional execution occurs seamlessly since the processor will re-execute the HLE region without actually doing elision, and then execute the RTM instructions.

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