如何获得可靠的Cortex M4短延迟 [英] How to obtain reliable Cortex M4 short delays
问题描述
我正在将一些代码从M3移植到使用3个NOP的M4，以在串行输出时钟更改之间提供非常短的延迟. M3指令集将NOP的时间定义为1个周期.我注意到，M4中的NOP并不一定会延迟任何时间. 我知道我将需要禁用编译器优化，但是我正在寻找一个低级命令，该命令将为我提供可靠的，可重复的时间. 实际上，在这种特殊情况下，串行经常被使用，并且速度可能很慢，但是我仍然想知道获得周期级延迟的最佳方法.
如果您需要非常短但确定性的至少"延迟，也许您可以考虑使用nop以外的其他具有确定性非零延迟的指令./p>
Cortex-M4 NOP 不一定是耗时的.
您可以将其替换为and reg, reg，或在上下文中大致等同于nop的名称.另外，切换GPIO时，您也可以重复I/O指令本身以强制达到最小状态长度(例如，如果GPIO写入指令至少花费5ns，则重复五次以获得至少25ns).如果您要在C程序中插入nops，这甚至可以在C中很好地工作(只需重复对端口的写入操作，如果它应为volatile，则编译器不会删除重复的访问权限.)
当然，这仅适用于非常短的延迟，否则，对于短暂的延迟(如其他人所提到的那样)，等待某个时序源的繁忙循环会更好地工作(它们至少需要采样时序源所需的时钟，目标，然后经历一次等待循环.
I am porting some code from an M3 to an M4 which uses 3 NOPs to provide a very short delay between serial output clock changes. The M3 instruction set defines the time for a NOP as 1 cycle. I notice that NOPs in the M4 do not necessarily delay any time at all. I am aware that I will need to disable compiler optimisation but I'm looking for a low level command that will give me reliable, repeatable times. In practice in this particular case the serial is used very occasionally and could be very slow but I'd still like to know the best way to obtain cycle level delays.
If you need such very short, but deterministic "at least" delays, maybe you could consider using other instructions than nop which have deterministic nonzero latency.
The Cortex-M4 NOP as described is not necessarily time consuming.
You could replace it to, say and reg, reg, or something coarsely equivalent to a nop in the context. Alternatively, when toggling GPIO, you could also repeat the I/O instructions themselves to enforce the minimal length of a state (such as if your GPIO writing instruction takes at least 5ns, repeat it five times to get at least 25ns). This could even work well within C if you were inserting nops in a C program (just repeat the writes to the port, if it's volatile as it should be, the compiler wouldn't remove the repeated accesses).
Of course this only applies to very short delays, otherwise for short delays, like mentioned by others, busy loops waiting for some timing source would work much better (they take at least the clocks required to sample the timing source, set up the target, and go through once the wait loop).
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