Verilog和有什么不一样！和〜? [英] What is the difference between Verilog ! and ~?

问题描述

因此，最终使我困扰了几天的bug是一段代码，应该将其评估为False，并将其评估为True.我的初始代码如下:

So it ended up that the bug that had kept me on for days, was a section of code that should have evaluated to False evaluating to True. My initial code went something like:

if(~x && ~y) begin
    //do stuff
end

即如果x不为1，y不为1，则执行操作.逐步调试程序，我意识到即使x为1，if语句中的表达式仍会导致结果为TRUE，并执行了后续代码.

i.e. If x is NOT ONE and y is NOT ONE then do stuff. Stepping through the debugger, I realized even though x was 1 the expression in the if-statement still resulted into TRUE and the subsequent code was executed.

但是，当我将语句更改为:

However, when I changed the statement to:

if(x == 0 && y == 0) begin
//do stuff
end

并尝试:

if(!x && !y) begin
//do stuff
end 

if语句中的代码未评估，这是预期的行为.我知道〜是一个按位取反和！逻辑否定，但是(〜x&〜y)和(！x&！y)不应评估同一件事吗?恐怕代码库太大，所以我不能在这里粘贴它，但这是我所做的唯一更改，目的是使代码按预期工作.谢谢.

the code within the if-statement was not evaluated which was the expected behaviour. I understand that ~ is a bitwise negation and ! a logical negation, but shouldn't (~x && ~y) and (!x && !y) evaluate to the same thing? I'm afraid the codebase is too large, so I can't paste it here, but this was the only alteration I made to make the code to work as I intended. Thanks.

作为回应，针对以下评论之一，我创建了一个测试案例来测试此行为:

In response, to one of the comments below, I have created a test-case to test this behaviour:

`timescale 10ns/1ns

module test_negation();
        integer x, y;

    initial begin
        x = 1; y = 0;

        if(~x && ~y) begin
            $display("%s", "First case executed");
        end

        if(!x && !y) begin
            $display("%s", "Second case executed");
        end

        if(x == 0 && y == 0) begin
            $display("%s", "Third case executed");
        end
    end endmodule

奇怪的是，打印了第一个案例已执行"以确认我观察到的原始行为.

And strangely enough, "First case executed" is printed to confirm the original behaviour I observed.

推荐答案

我明白了.上面代码中的变量"x"是Verilog整数(integer x;).但是，整数变量由Verilog表示为32位整数.因此，即使x如我所观察到的那样为"1"，〜x也不会导致"0"而是"11111111111111111111111111111111110"！因此，第一案被执行就不足为奇了.我的错.感谢您提供所有答案.

I see. The variable "x" in the above code was a Verilog integer (integer x;). However, an integer variable is represented by Verilog as a 32-bit integer number. So even though x was "1" as I had observed, ~x will not result in "0" but in "11111111111111111111111111111110"! And so it's no surprise that the First Case was executed. My fault. Thanks for all the answers.

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