x86-SSE指令是否具有自动发布获取指令？ [英] Does x86-SSE-instructions have an automatic release-acquire order?

问题描述

我们从C11-memory_order中了解到： http：//en.cppreference。 com / w / c / atomic / memory_order

As we know from from C11-memory_order: http://en.cppreference.com/w/c/atomic/memory_order

与C ++ 11-std :: memory_order相同： http://en.cppreference.com/w/cpp/atomic/memory_order

And the same from C++11-std::memory_order: http://en.cppreference.com/w/cpp/atomic/memory_order

在强排序系统（ x86 ，SPARC，IBM大型机）上，
发布-获取顺序是自动的。对于此同步模式，不会发出其他CPU指令
，仅会影响某些编译器
的优化（例如，禁止编译器
将非原子存储移至原子存储之外，释放或执行
的非原子负载早于获取原子负载）

On strongly-ordered systems (x86, SPARC, IBM mainframe), release-acquire ordering is automatic. No additional CPU instructions are issued for this synchronization mode, only certain compiler optimizations are affected (e.g. the compiler is prohibited from moving non-atomic stores past the atomic store-release or perform non-atomic loads earlier than the atomic load-acquire)

但是对于x86-SSE确实如此-指令（[NT]-非时间指令，我们必须始终使用L / S / MFENCE除外）？

But is this true for x86-SSE-instructions (except of [NT] - non-temporal, where we always must use L/S/MFENCE)?

这里说，这些说明...不需要向后兼容，并且内存顺序是未定义的。可以认为，在需要时，严格的可订购性使它与旧版本的x86处理器兼容，但是新命令，即SSE（[NT]除外）-会自动取消获得订单的订单，是吗？

Here said, that "sse instructions ... is no requirement on backwards compatibility and memory order is undefined". It is believed that the strict orderability left for compatibility with older versions of processors x86, when it was needed, but new commands, namely SSE(except of [NT]) - deprived automatically release-acquire of order, is it?

推荐答案

此处摘录自《英特尔软件开发人员手册》第3卷，第8.2.2节（2014年9月的版本325384-052US）：

Here is an excerpt from Intel's Software Developers Manual, volume 3, section 8.2.2 (the edition 325384-052US of September 2014):

• 读取未与其他重新排序


• 较早的读取不会对写入进行重新排序。


• 对内存的写入不会与其他写入进行重新排序，但以下情况除外：
  
  
  
  • 用CLFLUSH指令执行；
  
  
  • 流式存储（写入），用非临时移动指令执行（ MOVNTI，MOVNTQ，MOVNTDQ，MOVNTPS和MOVNTPD）；
  
  
  • 字符串操作（请参阅第8.2.4.1节）。
  
  

• Reads are not reordered with other reads.
• Writes are not reordered with older reads.
• Writes to memory are not reordered with other writes, with the following exceptions:
  • writes executed with the CLFLUSH instruction;
  • streaming stores (writes) executed with the non-temporal move instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD); and
  • string operations (see Section 8.2.4.1).

前三个项目符号描述了发布获取顺序，其中明确列出了例外。如您所见，例外列表中仅包含缓存控制指令（ MOVNT * ），而其余的SSE / SSE2和其他矢量指令则遵循常规的内存排序规则，并且不需要使用 [LSM] FENCE 。

The first three bullets describe the release-acquire ordering, and the exceptions are explicitly listed there. As you might see, only cacheability control instructions (MOVNT*) are in the exception list, while the rest of SSE/SSE2 and other vector instructions obey to the general memory ordering rules, and do not require use of [LSM]FENCE.

这篇关于x86-SSE指令是否具有自动发布获取指令？的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！