指令如何适合x86上的指令寄存器？ [英] How do instructions fit in the instruction register on x86?

问题描述

我了解到x86 CPU具有1到15个字节的可变指令长度。另一方面，x86字长为32位，这意味着所有寄存器（包括保存实际指令的指令寄存器）均为32位宽（4字节）。

I read that x86 CPUs have a variable instruction length of 1 to 15 bytes. On the other hand, it is also written that the x86 word size is 32 bits, that means all registers, including the instruction register which holds the actual instruction, are 32 bits wide (4 Bytes).

这意味着指令可以比指令寄存器更宽。这如何适应？此外，我了解到在执行一条指令后，指令计数器将不加跳转地增加4。这意味着它在假设每个指令为4个字节长的情况下运行。

That means the instructions can be wider than the instruction register. How does this fit? Further more, I learned that after executing an instruction, without jumping, the instruction counter is incremented by 4. That means it operates with the assumption that every instruction is 4 bytes long. How is this right?

我希望有人能为我澄清这一点。

I hope that someone could clarify this for me.

推荐答案

x86具有相当复杂的操作码解析器，具有多个状态。首先，它会寻找传统的前缀，例如 REP ， LOCK ，地址和操作数覆盖前缀，并且可能只是设置内部标志。然后，它查找必需的和rex前缀，并可能设置其他内部标志。之后，解析器需要实际的指令...或0x0f前缀以获取更多指令。甚至该指令字节也可能包含其他数据，例如，寄存器可以在那里编码，因此，根据指令的最高三位（0bxxx .....），解析器必须确定指令是否对寄存器进行了编码（例如0b000xxx110：按xxx ，其中xxx是 es ， cs ， ss 或 ds ）。根据指令，解析器然后查找ModR / M字段并对其进行评估。当此ModR / M字段指示有一个SIB字段时，您猜怎么着？它会评估SIB字段。根据指令的不同，ModR / M字段或SIB字段可能会有立即偏移量和/或末尾的立即值。

The x86 has a quite complex opcode-parser with multiple states. First it looks for the legacy prefixes like REP, LOCK, address- and operand-override-prefixes and probably just sets internal flags. Then it looks for mandatory and rex prefixes and probably sets other internal flags. After this, the parser expects the actual instruction...or a 0x0f-prefix for more instructions. Even this instruction-byte may contain other data, e.g.registers could be encoded there, so depending on the highest three bits (0bxxx.....) of the instruction, the parser has to decide, whether the instruction encodes an register (e.g. 0b000xxx110: push xxx, where xxx is es, cs, ss or ds) or not. depending on the instruction, the parser then looks for an ModR/M-field and evaluates this. When this ModR/M-field indicates, there is an SIB-field to, then, guess what?, it evaluates the SIB-field. There could be, depending on the instruction, ModR/M-field or SIB-field, an immediate offset and/or an immediate value at the end.

我不知道处理器实际上存储了这些东西。也许有一个用于指令的寄存器，一个标志寄存器，一个用于存储目标寄存器号的寄存器，一个用于立即数的寄存器以及某种形式的已用地址。

I do not know, how the processor actually stores this stuff. Maybe there is an register for the instruction, a flag-register, a register, where the destination-register-number is stored, a register for the immediate value and some kind of representation of used addresses.

无论如何，您可能不会为RISC处理器听到此指令寄存器，即使仅由于通用寄存器的长度为64位，其他寄存器也不必具有此大小。例如。 Streaming SIMD扩展提供了大小为128位的xmm寄存器。它们可能包含完整的15字节有效x86指令。

Anyway, there is not this instruction-register you may heard for RISC-processors and even if, just because the length of general registers is 64bit, other registers does not have to be this size. E.g. the Streaming SIMD Extensions provide xmm-registers, that are 128bit in size. They could contain a full 15-byte valid x86-instruction.

您可以找到第5页的此解析器的结构在这里。

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