计算缓存对处理器总体CPI的影响 [英] Calculating the effect of the cache on the overall CPI of the processor

问题描述

在给定基本CPI，L1和L2缓存的未命中率％以及L1，L2和内存的访问时间的情况下，如何计算L1和L2缓存对处理器总体CPI的影响

要查找L1缓存的CPI，您可以使用：

  CPI = BaseCPI +（％的L1小姐x内存访问时间）
  

所以我想对于L2来说是这样的： / p>

  CPI = BaseCPI +（L1丢失的百分比x L2访问时间）+（我为x内存访问时间感到困惑的百分比） 
  

如何找到第二个百分比？

我知道这与L2的未命中率％有关，但是是否必须乘以L1的未命中率％，因为L2的未命中只会在L1的未命中之后发生？

L2总访问次数是内存访问总数* L1的未命中率。

因此，您的计算应为-

  CPI = BaseCPI +（L1丢失百分比x L2访问时间）+（％L1丢失率x％L2丢失率x内存访问时间）
  

或更方便：

  CPI = BaseCPI +（L1丢失的百分比x（L2访问时间+（L2丢失率x内存访问时间））））
  

这也不是很准确-您没有指定内存操作的速率，上面的假设是每条指令都要查找缓存，这有点夸张。如果您在程序中有一定的加载/存储速率，则也必须考虑到它。

在现实世界中，您还需要在L2访问总数中添加以下内容：

1. L1写回


2. 代码读取（如果来自）单独的指令L1


3. 硬件预取

但是这些通常在简单的计算中会被忽略，因为（而且您不知道已修改行的百分比，因此无论如何您都无法推断出将有多少个写回）。

更多说明-它不是实际上缓存的CPI ，缓存本身不执行指令或不在乎其时间。正确的说法是-缓存（或任何其他功能）对处理器总体CPI的影响。

How does one calculate the effect of L1 and L2 cache's on the overall CPI of the processor given base CPI, miss rate % of L1 and L2 caches and access times of L1, L2, and the memory

To find the CPI of L1 cache you would use:

CPI = BaseCPI + (% of L1 Miss x Memory Access Time)

So I imagine that for L2 it would be something like:

CPI = BaseCPI + (% of L1 Miss x L2 Access Time) + ( % which I am confused about x Memory Access time)

How would one go about finding that second percentage?

I know that is has to do with the miss rate % of L2 but is it necessary to multiply by L1 Miss Rate % since L2 Miss will only happen after an L1 miss?

解决方案

Yes, the miss rate of the L2 means the % of misses out of total L2 accesses. Total L2 accesses are the total number of memory accesses * miss rate of the L1.

So, your calculation should be -

CPI = BaseCPI + (% of L1 Miss x L2 Access Time) + ( %L1 miss rate x % L2 miss rate x Memory Access time)  

or more conveniently:

CPI = BaseCPI + (% of L1 Miss x (L2 Access Time + (%L2 miss rate x Memory Access time)))

That's also not very accurate - you didn't specify the rate of memory operations, the above is assuming that every instruction is going to lookup the caches, which is a bit exaggerated. If you have a rate of loads/stores in the program you'll have to factor it in as well.

By the way, in the real world you also need to add the following to the total L2 accesses:

1. L1 writebacks
2. Code reads, if originating from a separate instruction L1
3. HW prefetching

But these are usually ignored in simple calculations as this (and you don't know the % of modified lines, so you can't deduce how many writebacks you'll have anyway).

One more note - it's not really The CPI of the cache, the cache itself doesn't perform instructions or cares about their timing. The proper term would be - The effect of the cache (or any other feature) on the overall CPI of the processor.

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