VHDL时钟控制的LED序列第2部分 [英] VHDL clocked LED Sequence Part 2

问题描述

我必须编写一个程序，该程序在每个时钟脉冲将一个LED序列更改为一个序列。

I have to write a program that changes an LED sequence at each clock pulse for one sequence.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


entity REG_LED is
 PORT(CLK:      IN  std_logic;              -- CLK input
 LEDS:      Out std_logic_vector (4 downto 0):= "11111"); -- initialise output
End REG_LED;

ARCHITECTURE behavioral OF REG_LED IS
 SIGNAL Temp:   std_logic_vector (3 downto 0):= "0000"; -- initailise comparison signal
BEGIN

CLK_Process:    PROCESS (CLK)   -- begin 
BEGIN 

if rising_edge(CLK) Then
       Temp <= Temp + 1 ;   
END IF;

iF TEMP > "1000" THEN
    Temp <= "XXXX";
End IF;

END PROCESS ;

LED_PROCESS: Process (Temp) --

BEGIN

    Case Temp is

        When "0000" =>
            LEDS <= "11111";
        When "0001" =>
            LEDS <= "00001";
        When "0010" =>
            LEDS <= "00001";
        When "0011" =>
            LEDS <= "11111";
        When "0100" =>
            LEDS <= "00000";
        When "0101" =>
            LEDS <= "11111";
        When "0110" =>
            LEDS <= "00100";
        When "0111" =>
            LEDS <= "01010";
        When "1000" =>
            LEDS <= "10001";
        When others => 
            LEDS <= "10001";
    End Case;               

End Process;
END behavioral; 

这看起来更像您所期望的吗？它模拟但我无法测试代码的综合，因为我现在有硬件对其进行测试。或者，如果有办法，因为我是VHDL的新手，我还没有弄清楚如何测试它。

Does this look more like what you would expect? it simulates but i cant test the synthesis of the code as i have now hardware to test it with. Or if there is a way because I'm new to VHDL I haven't worked out how to test it.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


entity REG_LED is
PORT(CLK:       IN  std_logic;              -- CLK input
     LEDS:      Out std_logic_vector (4 downto 0):= "11111"); -- initialise output
End REG_LED;

ARCHITECTURE behavioral OF REG_LED IS
SIGNAL Temp:    integer range 0 to 9:= 0; -- initailise comparison signal
BEGIN

    CLK_Process:    PROCESS (CLK)   -- begin 
    BEGIN 

    if rising_edge(CLK) Then
        if Temp = 8 then
            Temp <= 0; -- State Count Reset
        else
            Temp <= Temp + 1 ; -- State Count
        End if;

    END IF;

    END PROCESS ;

    LED_PROCESS: Process (Temp) -- LED Outputs based on Temp count

    BEGIN

        Case Temp is

            When 0 =>
                LEDS <= "11111"; -- S0
            When 1 =>
                LEDS <= "00001"; -- S1
            When 2 =>
                LEDS <= "00001"; -- S2
            When 3 =>
                LEDS <= "11111"; -- S3
            When 4 =>
                LEDS <= "00000"; -- S4
            When 5 =>
                LEDS <= "11111"; -- S5
            When 6 =>
                LEDS <= "00100"; -- S6
            When 7 =>
                LEDS <= "01010"; -- S7
            When 8 =>
                LEDS <= "10001"; -- S8

            When others => 
                LEDS <= "11111"; -- Restart Sequence
        End Case;               

    End Process;

推荐答案

这段代码相当不错，但这是一回事需要注意的地方：

This code is pretty good, but here is one thing that needs attention:

这两个软件包都不是：

use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

实际上，您的代码仅使用 std_logic_unsigned 包；它根本没有使用 numeric_std 包。 std_logic_unsigned 包为 std_logic_vector 类型定义了各种算术运算符。这些假定为 unsigned 算术，因此为名称。您在此行中使用 std_logic_unsigned 包：

In fact, your code is only using the std_logic_unsigned package; it is not making use of the numeric_std package at all. The std_logic_unsigned package defines various arithmetic operators for the std_logic_vector type. These assume unsigned arithmetic, hence the name. You are making use of the std_logic_unsigned package in this line:

Temp <= Temp + 1 ;   

对于新代码，您应该真正使用 numeric_std 包，而不是 std_logic_unsigned 包。为此，您必须将 Temp 的类型更改为 unsigned 。类型 unsigned 只是 std_logic 的数组，如 std_logic_vector ，

For new code, you should really use the numeric_std package, not the std_logic_unsigned package. To do this, you would have to change the type of Temp to unsigned. Type unsigned is just an array of std_logic like std_logic_vector, but as its name implies, it is used to implement unsigned arithmetic.

因此，我会

i）删除以下行：

use ieee.std_logic_unsigned.all;

ii）更改此行：

SIGNAL Temp:   std_logic_vector (3 downto 0):= "0000"; -- initailise comparison signal

至：

SIGNAL Temp:   unsigned (3 downto 0):= "0000"; -- initailise comparison signal

iii）（正如Scary Jeff指出的）思考 Temp 到 XXXX 的操作。您是否不想让计数器将整数环绕到 0000 ？如果要使其冻结为 1000 ，则需要一些其他代码。无论如何，绝不要将任何代码置于时钟的 rising_edge 之外。 （它不符合我向您展示的模板。您希望此代码产生什么逻辑？）

iii) (as Scary Jeff points out) think about what the assignment of Temp to "XXXX" is doing. Wouldn't you prefer your counter to wrap round to "0000"? If, if you want it to freeze at "1000", you'll need some different code. In any case, never put any code outside the test for the rising_edge of clock. (It doesn't comply with the template I showed you. What logic would you expect to be produced by this code?)

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