VHDL直接比较向量 [英] VHDL directly comparing vectors

问题描述

我想知道是否有可能直接比较两个向量，而不是一点一点地看它们。

I was wondering if its possible to directly compare 2 vectors with eachother instead of just looking at them bit by bit.

例如：

entity Comparator is
port(a,b in: std_logic_vector (2 downto 0);
     out1, out2 out: std_logic);
end Comparator;

architecture behavioural of Comparator1 is
begin
    if a = b then
        out1 <= '1'
    else if /= then
        out2 <= '1'
    end if;
end behaviour;

这可能吗？

推荐答案

是的，您可以直接比较两个具有相同类型和子类型指示的数组类型。

The answer is yes, you can compare two array types of the same type and subtype indication directly.

但是示例代码无效。

表达式 a = b 是布尔值。您可以通过分配 out1 和 out2 将其转换为std_logic。在这种情况下，if语句必须位于process语句中。同样，您也不需要两个输出：

The result of the expression a=b is boolean. You convert that to std_logic by assigning out1 and out2. An if statement in this context has to be in a process statement. Also you don't need two outputs:

architecture foo of Comparator1 is
begin
UNLABELED:
    process (a,b)
    begin
        if a = b then
            out1 <= '1';
        else 
            out1 <= '0';
        end if;
    end process;
end architecture;

可选的并发信号分配语句，即条件信号分配，其处理过程与上述等效： / p>

Alternative a concurrent signal assignment statement, a conditional signal assignment that has an equivalent process to that above:

architecture fum of Comparator1 is
begin
UNLABELED:
    out1 <= '1' when a = b else '0';
end architecture;

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