在VHDL .....如何计算向量的前导零? [英] In VHDL ..... how to count leading zeros of vector?

问题描述

我正在VHDL项目中工作，因此在计算向量长度时遇到了问题.我知道向量的length属性，但是这不是我要寻找的长度.例如，我有std_logic_vector

I'm working in a VHDL project and I'm facing a problem to calculate the length of vector. I know there is length attribute of a vector but this not the length I'm looking for. For example, I have std_logic_vector

    E : std_logic_vector(7 downto 0);  

然后

    E <= "00011010";

所以，len = E'length = 8，但是我不是在找这个.我想在丢弃最左边的零后计算len，所以len = 5;

so, len = E'length = 8 but I'm not looking for this. I want to calculate len after discarding the left most zeros , so len = 5;

我知道我可以通过从左到右检查"0"位来进行循环，并在出现"1"位时停止.但这效率不高，因为我有1024位或更多位，这会减慢电路速度.那么，有什么方法或算法可以有效地计算长度吗?例如使用log(n)级门的组合门(其中n =位数).

I know that I can use for loop by checking "0"s bits from left to right and stop if "1" bit occur. But that's not efficient, because I have 1024 or more of bits and that will slow my circuit. So is there is any method or algorithm to calculate the length in efficient way? Such as using combinational gates of log(n) level of gates, ( where n = number of bits ).

推荐答案

对位数"的处理与对数(以2为底)非常相似.

What you do with your "bit counting" very similar to the logarithm (base 2).

在VHDL中通常使用它来确定表示一个信号需要多少位.例如，如果要在RAM中存储多达N个元素，则寻址该RAM所需的位数为ceil(log2(N)).为此，我使用:

This is commonly used in VHDL to figure out how many bits are required to represent a signal. For example if you want to store up to N elements in RAM, the number of bits required for addressing that RAM is ceil(log2(N)). For this I use:

function log2ceil(m:natural) return natural is
begin -- note: for log(0) we return 0
    for n in 0 to integer'high loop
        if 2**n >= m then
            return n;
        end if;
    end loop;
end function log2ceil;

通常，您希望在合成时使用常量来执行此操作，而速度无关紧要.但是，如果您确实需要，也可以生成FPGA逻辑.

Usually, you want to do this at synthesis time with constants, and speed is no concern. But you can also generate FPGA logic, if that's really what you want.

正如其他人所提到的，VHDL中的"for"循环仅用于生成查找表，由于较长的信号路径，它可能会变慢，但仍仅占用一个时钟.可能发生的事情是您的最大时钟频率下降了.通常，只有在大于64位(提到了1024位)的矢量上运行并且时钟速度超过100MHz时，这才是问题.也许合成器已经告诉您这是您的问题，否则我建议您先尝试.

As others have mentioned, a "for" loop in VHDL is just used to generate a lookup table, which may be slow due to long signal paths, but still only takes a single clock. What can happen is that your maximum clock frequency goes down. Usually this is only a problem if you operate on vectors larger than 64bit (you mentioned 1024 bits) and clocks faster than 100MHz. Maybe the synthesizer already told you that this is your problem, otherwise I suggest you try first.

然后，您必须将操作分成多个时钟，并将一些中间结果存储到FF中. (我会先忘记尝试通过重新排列代码来使合成器智能化.查找表是一个表.在此表中生成值的原因为何重要呢?但是请确保告诉合成器无关紧要"(如果有的话).

Then you have to split up the operation over multiple clocks, and store some intermediate result into a FF. (I would upfront forget about trying to outsmart the synthesizer by rearranging your code. A lookup-table is a table. Why should it matter how you generate the values in this table? But make sure you tell the synthesizer about "don't care" values if you have them.)

如果您关注速度，请使用第一个时钟并行检查所有16位块(彼此独立)，然后使用第二个时钟周期将所有16位块的结果合并为一个结果.如果您担心FPGA逻辑的数量，可以实现一个状态机，该状态机在每个时钟周期检查一个16位块.

If speed is your concern, use the first clock to check all 16bit blocks in parallel (independent of each other), and then use a second clock cycle to combine the results of all 16bit blocks into a single result. If the amount of FPGA logic is your concern, implement a state machine that checks a single 16bit block at every clock cycle.

但是要小心，不要在这样做时重新发明CPU.

But be careful that you don't re-invent the CPU while doing that.

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