关于DMA和CPU并发 [英] On DMA and CPU Concurrency

问题描述

我想知道在设备的DMA控制器进行内存操作时，CPU可以处理/执行哪种操作，以提高并发水平？如果CPU缓存/寄存器为空，那么如何在不进行DMA插入的情况下获取另一条指令

Thx

解决方案

通常，在大型 ¹ 硬件上，在进行DMA时CPU可以执行或多或少的任何操作。通常，它只是继续在操作系统的控制下正常执行正在运行的进程或内核任务。

关于您的问题：

...如果CPU高速缓存/寄存器为空，如何在不进行DMA插入的情况下获取另一条指令
[？]

据我了解，您在问如果CPU需要访问内存会发生什么情况。通常，CPU通常不仅仅在寄存器或缓存为空时频繁访问存储器。当进行DMA时，此活动可以或多或少地正常进行 ² 。存储器总线通常已经被多个设备共享，包括多个支持DMA的设备，PCI卡，多个内核或多个CPU。 内存控制器负责接受并满足所有这些请求，包括在此之后进行仲裁。 / p>

因此，您正确的是，当DMA和CPU访问内存时，可能会有某种交错，就像在两个内核（甚至两个逻辑）上可能发生的那样在同一核心上运行的多个线程）访问内存。实际上，它的工作方式取决于DRAM的组织方式，内存控制器的工作方式（以及有多少个内存控制器）以及许多其他细节，但总的来说，您希望现代内存系统具有高度并行性-能够维持多个流访问并通常接近RAM施加的带宽限制。

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¹ 意味着比嵌入式微控制器还大的东西。例如，即使移动CPU也符合资格。

² 通过通常我的意思是使用了正常的机制，您可以期望内存访问工作，但性能不会受到影响。 CPU的内存访问将与DMA访问（以及其他CPU，PCI设备（例如视频卡等）的其他访问）竞争，并且速度可能会变慢-但是在合理的硬件上，它不必等到DMA完成！

I wondered what sort of operations can CPU handle/perform while a memory operation is in progress by a DMA-controller of a device, to increase the level of concurrency? And if the CPU cache/registers is empty, how another instruction can be fetched without interleaving DMA in progress

Thx

解决方案

It general, on big¹ hardware, the CPU can do more or less anything while a DMA is in progress. In general, it simply continues with normal execution of running processes or kernel tasks under the control of the OS.

In regards to your question:

... if the CPU cache/registers is empty, how another instruction can be fetched without interleaving DMA in progress[?]

As I understand it, you are asking what happens if the CPU needs to access memory. In general, the CPU is usually accessing memory frequently, not only when "registers or caches are empty". This activity can proceed more or less normally² when a DMA is in progress. The memory bus is already generally shared by several devices, including multiple DMA-capable devices, PCI cards, multiple cores or multiple CPUs. The memory controller is responsible for accepting and fulfilling all these requests, which include arbitrating between then.

So you are correct that there may be some type of "interleaving" when both DMA and the CPU access memory, just as this may occur when two cores (or even two logical threads running on the same core) access memory. How it works out in practice depends on how the DRAM is organized, how the memory controller works (and how many are present) and many other details, but in general you expect modern memory systems to be highly parallel - capable of sustaining multiple streams of accesses and often approaching the bandwidth limits imposed by RAM.

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¹These days that pretty much means anything bigger than an embedded microcontroller. E.g., even mobile CPUs qualify.

²By normally I mean the normal mechanisms are used and you can expect memory access to work, but not that performance won't be affected. The memory access by the CPU will be competing with the DMA access (and perhaps other access by other CPUs, PCI devices such as video cards, etc) and will likely be slower - but on reasonable hardware it certainly won't have to wait until the DMA finishes!

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