Verilog驱动信号在同一根导线上 [英] verilog driving signals on the same wire

问题描述

我通过互联网浏览，找不到针对我问题的清晰简洁的答案。我想知道如果在同一根导线上驱动相同强度的信号会发生什么情况，其中一个是逻辑1，另一个是逻辑0？如果我想根据具体情况缺少一个更好的词而希望信号获胜怎么办？

I looked through internet and couldn't find a clear and concise answer to my question. I want to know what'll happen if I drive same strength signals onto the same wire, one of them being logic 1 and the other being logic 0? What do I do if I want a signal to "win", for lack of a better word, depending on the situation?

推荐答案

根据您的评论，听起来您需要三态总线。驱动三态总线的基本结构是：

Based on your comment, it sounds like you want a three-state bus. The basic structure to drive a three-state bus is:

assign bus = enable ? out : 1'bz;

驱动总线的每个模块都有这种形式的驱动程序。任何时候只有一个模块可以启用其启用；总线协议应定义如何确定总线所有权。例如，像I2C这样的串行总线有一个主和一个从。主机总是先讲话，而从机只有在主机请求后才讲话。

Each module driving the bus has a driver of this form. Only one module may have its enable asserted at any time; the bus protocol should define how ownership of the bus is decided. For example, serial buses like I2C have a "master" and a "slave"; the master always talks first, and the slave only talks after it has been requested to by the master.

如果您不希望在无人驾驶时总线浮动（在模拟中，它显示为Z值），则可以将总线声明为 tri0 或 tri1 ，而不是常规的 wire 。

If you don't want the bus to float when nothing is driving (in simulation, this shows up as a Z value), you can declare the bus as tri0 or tri1 rather than a regular wire.

如果多个模块同时声明了启用，或者如果您有多个标准 assign bus = out; 驱动程序试图在总线上驱动不同的值，这称为争用。这将在仿真中显示为X值，并可能损坏物理设备中的驱动程序。

If multiple modules have the enable asserted at the same time, or if you have multiple standard assign bus = out; drivers attempting to drive different values on the bus, it is known as "contention". This will show up as an X value in simulation, and could result in damage to the drivers in a physical device.

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