环形计数器测试波形的不确定输出 [英] Undefined output of Ring Counter Test waveform

问题描述

我已经使用D型触发器为4位环形计数器建模。

I have modeled 4 bit Ring Counter using D Flip Flop.

D触发器在单独的文件中，包含在我的工作区中。 D触发器正常工作（给出正确的输出波形）。

The D flip flop is in separate file, included in my workspace. The D flip flop works correctly (gives correct output waveform).

这是环形计数器的代码：

This is the code of ring counter:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ring4counter is
    port (
        clk: std_logic;
        output: out std_logic_vector(3 downto 0));
end ring4counter;

architecture ring4counter_arch of ring4counter is
    component dff
    port (
        clk: std_logic;
        d: in std_logic;
        q: out std_logic;
        qbar: out std_logic);
    end component;

    signal temp:std_logic_vector(3 downto 0):=(others=>'0');
begin
    r1: dff port map(clk, temp(3), temp(0));
    r2: dff port map(clk, temp(0), temp(1));
    r3: dff port map(clk, temp(1), temp(2));
    r4: dff port map(clk, temp(2), temp(3));
    output <= temp;
end ring4counter_arch;

以下是Ring计数器的测试台代码：

Here is the testbench code for Ring counter:

library ieee;
use ieee.std_logic_1164.all;

entity ring4_tb is end ring4_tb ;

architecture arch of ring4_tb is
    component tbc is
    port (
        clk: std_logic;
        output: out std_logic_vector(3 downto 0));
    end component ;

    component dff
    port (
        clk: std_logic;
        d: in std_logic;
        q: out std_logic;
        qbar: out std_logic);
    end component;

    constant period : time := 50 ns ;

    signal clk      : std_logic := '0' ;    
    signal done     : boolean := false ;
    signal output   : std_logic_vector(3 downto 0) ;

    shared variable cycle : natural := 0 ;

    signal temp:std_logic_vector(3 downto 0):=(others=>'0');

begin
-- this is the unit under test
    u1: tbc
    port map(
        clk    => clk,
        output => output) ;

    clkprocess: process(done, clk)
    begin
    if (not done) then
        if (clk = '1') then
        cycle := cycle + 1 ;
        end if ;
        clk <= not clk after period / 2 ;
    end if ;
    end process ;

    r1: dff port map(clk, temp(3), temp(0));
    r2: dff port map(clk, temp(0), temp(1));
    r3: dff port map(clk, temp(1), temp(2));
    r4: dff port map(clk, temp(2), temp(3));
    output <= temp;

    testbench: process
    begin
    wait until (clk = '0') ;
    temp <= "1000";
    wait for period*4 ;

    done <= true ;      -- force the clock process to shutdown
    wait ;          -- this waits forever
    end process ;
end arch ;

但所有位的输出波形均为 U。
我要去哪里了？

But the waveform for 'output' is 'U' for all bits. Where am I going wrong?

推荐答案

在testbench进程中，当您尝试将temp初始化为 1000时，触发器也仍在驱动温度信号，因此您实际上正在进行总线争夺。

In the testbench process when you are trying to initialize temp to "1000", the flip flops are still driving the temp signal as well, so you effectively have a bus fight going on.

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