为什么分支延迟槽已过时或过时？ [英] Why is the branch delay slot deprecated or obsolete?
问题描述
当我阅读RISC-V用户级ISA手册时，我注意到它说： OpenRISC具有条件代码和分支延迟时隙，这会使更高性能的实现复杂化。因此RISC-V没有分支延迟槽 RISC-V用户级ISA手册链接。此外，维基百科说，大多数新的RISC设计都省略了分支延迟槽。为什么大多数较新的RISC体系结构会逐渐省略分支延迟槽？
Fallacy：您可以设计一个完美的体系结构。
所有体系结构设计都需要在上下文中进行权衡。一套硬件和软件技术。随着时间的流逝，这些技术可能会发生变化，并且在做出决定时可能是正确的决定看起来像是错误。 （...）RISC集中营中的一个例子
是延迟分支。用五级流水线控制流水线
的危害很简单，但是对于具有较长
流水线且每个时钟周期发出多个指令的处理器来说，这是一个挑战。
实际上，就软件而言，延迟分支仅具有缺点，因为它会使程序更难阅读，效率也较低，因为插槽是
在硬件方面，这是一项技术决策，在80年代是有意义的，当时管道是5或6个阶段，没有办法避免单周期分支惩罚。
但是目前，管道要复杂得多。在最近的奔腾®架构上，分支惩罚为15-25个周期。因此，一个指令延迟分支是没有用的，并且试图用15条指令延迟分支来隐藏该延迟槽是毫无意义的，并且显然是不可能的（这将破坏指令集的兼容性）。
我们已经开发了新技术。分支预测是一项非常成熟的技术。使用目前的分支预测器，错误预测远远低于具有无用（ nop ）延迟时隙的分支数量，因此即使在6周期计算机上（例如， nios-f）。
因此，延迟分支在硬件和软件方面的效率较低。没有理由保留它们。
When I reading RISC-V User-Level ISA manual,I noticed that it said that "OpenRISC has condition codes and branch delay slots, which complicate higher performance implementations." so RISC-V don't have branch delay slot RISC-V User-Level ISA manual link. Moreover,Wikipedia said that most of newer RISC design omit branch delay slot. Why most of newer RISC Architecture gradually omit branch delay slot?
Citing Henessy and Patterson (Computer architecture and design, 5th ed.)
Fallacy : You can design a flawless architecture.
All architecture design involves trade-offs made in the context of a set of hardware and software technologies. Over time those technologies are likely to change, and decisions that may have been correct at the time they were made look like mistakes. (...) An example in the RISC camp is delayed branch. It was a simple matter to control pipeline hazards with five-stage pipelines, but a challenge for processors with longer pipelines that issue multiple instructions per clock cycle.
Indeed, in terms of software, delayed branch only has drawbacks as it makes programs more difficult to read and less efficient as the slot is frequently filled by nops.
In terms of hardware, it was a technological decision that has some sense in the eighties, when pipeline was 5 or 6 stages and there was no way to avoid the one cycle branch penalty.
But presently, pipelines as much more complex. Branch penalty is 15-25 cycles on recent pentium μarchitectures. One instruction delayed branch is thus useless and it would be a nonsense and clearly impossible to try to hide this delay slot with a 15 instructions delayed branch (that would break instruction sets compatibility).
And we have developed new technologies. Branch prediction is a very mature technology. With present branch predictors, misprediction is by far lower than the number of branches with a useless (nop) delay slot and is accordingly more efficient, even on a 6 cycles computer (like nios-f).
So delayed branches are less efficient in hardware and software. No reason to keep them.
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