如何加快VHDL中的数学运算速度? [英] How can I speed up my math operations in VHDL?

问题描述

我目前在75MHz像素时钟的上升沿进行一些计算，以在屏幕上输出720p视频.一些数学运算(例如一些模)花费的时间太长(20 + ns，而75MHz为13.3ns)，所以我的时序约束得不到满足.我是FPGA的新手，但我想知道例如是否有一种方法可以以比当前像素时钟更快的速度运行计算，以便在75MHz时钟的下一个时钟周期完成计算.顺便说一下，我正在使用VHDL.

I have some calculations going on currently at rising edge of a 75MHz pixel clock to output 720p video on screen. Some of the math (like a few modulo) take too long (20+ns whereas 75MHz is 13.3ns) so my timing constraints are not met. I'm new to FPGAs but I'm wondering if for example there is a way to run the calculations at a faster speed than the current pixel clock in order to have them completed by the next tick of the 75MHz clock. I'm using VHDL by the way.

推荐答案

以下是一些技巧:

• 流水线-拆分逻辑以在多个时钟周期内运行
• 多循环路径-如果您不需要每个循环都提供答案，则可以告诉工具可以花更长的时间.需要注意的是，不要告诉工具错误的地方！
• 再想一想-例如，您是否真的需要在非常宽的x上执行x mod 3，还是可以使用连续更新的模3计数器?
• 使用更好的工具-与不使用供应商的合成器在相同代码上满足时序相比，我曾经遇到过使用昂贵的合成器在深层逻辑路径上满足时序的情况.

• Pipelining - split the logic up to operate over multiple clock cycles
• multi-cycle path - if you don't need the answer every cycle, you can tell the tools that it's OK for it to take longer. Care is required not to tell the tools the wrong thing though!
• Think again - for example, do you really need to do x mod 3 on very wide x, or could you use a continuously updated modulo 3 counter?
• Use better tools - I've had instances where I could meet timing on a deep-logic-path using an expensive synthesizer compared to not meeting timing on the same code using the vendor's synthesizer.

更极端的解决方案包括更换硅片，以使用更快的设备，更新的设备或更新的更快的设备.

More extreme solutions involve changing the silicon, for a faster device, or a newer device, or a newer, faster device.

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