"others => 0"的含义是什么?在任务说明中是什么意思? [英] What does "others=>'0'" mean in an assignment statement?

问题描述

cmd_register: process (rst_n, clk)
begin
   if (rst_n='0') then
    cmd_r<= (others=>'0');
   elsif (clk'event and clk='1') then
    cmd_r<=...;
   end if;
end process cmd_register;

我知道< ="指定分配，但是others是什么? =>是做什么的?

I know "<=" specifies assignment but what is others? And what does => do?

推荐答案

cmd_r被定义为 std_logic_vector 或 unsigned 或 signed 信号.让我们看看如何定义这种信号类型:

cmd_r is defined as a std_logic_vector, or unsigned or signed signal. let's see how this signal type are defined:

type std_logic_vector is array (natural range <>) of std_logic; 
type unsigned         is array (natural range <>) of std_logic; 
type signed           is array (natural range <>) of std_logic;

请注意，这3种类型与std_logic项目数组的定义相同.

Note that these 3 types have the same definition as an array of std_logic items.

当编码人员要在数组中定义具有相同值的多个项目时，语句"Others =>'0'"是VHDL的功能.

The statement "Others => '0'" is a feature of the VHDL when the coder want to defined several items in an array with the same value.

在您的示例中，数组中的所有std_logic项目都设置为"0".

In your example, all item std_logic in the array are set to '0'.

该语句的另一个应用是将某些项目设置为特定值，而将所有其他项目设置为默认值:

Another application of this statement is to set some items at a specific value and all others at a default value :

cmd_r <= (0      => '1',
          4      => '1',
          others => '0');

在这种情况下，位0和4设置为"1"，所有其他位设置为"0".

In this case, the bit 0 and 4 are set to '1' and all other bits are set to '0'.

最后一件事，不可能写这样的东西:

One last thing, it's NOT possible to write something like this :

  cmd_r <= (0          => '1',
            4 downto 2 => "111", -- this line is wrong !!!
            others     => '0');

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