FPGA大输入数据 [英] FPGA large input data

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本文介绍了FPGA大输入数据的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!

问题描述

我正在尝试向FPGA发送4 KB的字符串,最简单的方法是什么?

I am trying to send a 4 kilobyte string to an FPGA, what is the easiest way that this can be done?

是我正在使用的fpga的链接.我正在使用Verilog和Quartus.

This is the link for the fpga that I am using. I am using Verilog and Quartus.

推荐答案

问题的答案在很大程度上取决于将这些数据馈入FPGA的方式.即使您没有需要遵循的特定协议(SPI,以太网,USB等),也存在一个问题,即您需要多快接受数据以及数据必须传输多远.如果速度很慢,则可以使用带有并行数据总线和时钟的常规IO引脚创建一个简单的接口.如果速度更快,您可能需要探索使用高速串行接口和芯片上可用的特殊硬逻辑来处理这些速度.即使速度较慢,但​​数据需要传输一定距离,串行接口还是降低电缆成本的好主意.

The answer to your question depends a lot on what is feeding this data into the FPGA. Even if there isn't a specific protocol you need to adhere to (SPI, Ethernet, USB, etc.), there is the question of how fast you need to accept the data, and how far the data has to travel. If it's very slow, you can create a simple interface using regular IO pins with a parallel data bus and a clock. If it's much faster, you may need to explore using high speed serial interfaces and the special hard logic available on your chip to handle those speeds. Even if it's slower, but the data needs to travel over some distance, a serial interface may be a good idea to minimize cable costs.

我要在@gbuzogany的答案中添加一件事:您可能希望将FPGA中的该内存块配置为FIFO,以便您可以处理以与FPGA内部时钟不同的速率运行的数据输入时钟.

One thing I would add to @gbuzogany 's answer: You probably want to configure that block of memory in the FPGA as a FIFO so you can handle the data input clock running at a different rate than the internal clock of your FPGA.

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