信号电流无法合成，同步描述不良 [英] Signal current cannot be synthesized, bad synchronous description

问题描述

在Xillinx中合成此代码时出现错误.该错误是:

I have a error while Synthesize this code in Xillinx. This error is:

分析库中的实体(体系结构).
错误:Xst:827-"C:/Xilinx92i/Parking/Parking.vhd"行43:无法合成信号电流，同步描述错误.

Analyzing Entity in library (Architecture ).
ERROR:Xst:827 - "C:/Xilinx92i/Parking/Parking.vhd" line 43: Signal current cannot be synthesized, bad synchronous description.

entity Parking is port(
    A, B ,reset: in std_logic;
    Capacity : out std_logic_vector(7 downto 0));
end Parking;

architecture Behavioral of Parking is
    type state is (NoChange, Aseen, Bseen, ABseen, BAseen, Input, Output, Din, Dout);
    signal current, nxt : state ;
    signal counter : std_logic_vector (7 downto 0) := "00000000";
begin

    p1: process(A, B, reset)
    begin
        if reset = '1' then
            current <= Nochange;
        end if;

        if(A'event and A='1') then
            current <= nxt;
        end if;

        if(A'event and A='0') then
            current <= nxt;
        end if;

        if(B'event and B='1') then
            current <= nxt;
        end if;

        if(B'event and B='0') then
            current <= nxt;
        end if;
    end process;

    p2: process(current, A, B)
    begin
        case current is
            when Aseen =>
                if B='1' then
                    nxt <= ABseen;
                else
                    nxt <= NoChange;
                end if;

            when others =>
                nxt <= Nochange;
        end case;
    end process;

    Capacity <= counter;

end Behavioral;

推荐答案

错误错误的同步描述"通常意味着您描述了硬件中不存在的寄存器(带时钟的元素).

The error 'bad synchronous description' usually means that you have described a register (clocked element) that does not exist in the hardware.

对于您的代码，您具有:

In the case of your code, you have:

if(A'event and A='1') then
   current <= nxt;
end if;

if(A'event and A='0') then
    current <= nxt;
end if;

-- etc

在一个过程中.同步可合成过程通常只有一个时钟，因为在像FPGA这样的真实芯片设备中没有元件可以响应两个不同时钟上的事件.类似于您尝试实现的过程通常看起来像这样:

inside one process. Synchronous synthesisable processes will typically only have one clock, because there is no element in a real silicon device like an FPGA that can respond to events on two different clocks. A process like the one you are trying to implement would typically look something more like this:

process (clk)   
begin
    if (rising_edge(clk)) then
        if (a = '1') then
            current <= nxt;
        elsif (a = '0') then
            current <= nxt;
        end if;
    end if;
end process;

以这种方式实现需要您具备以下条件:

Implementing it this way requires that you have:

1. 系统中的时钟
2. 满足相对于此时钟的建立/保持时间的输入

旁注

如果您没有一个有意义的流程名称，则不必为它命名. process (clk)与p1 : process(clk)一样有效.

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