如何在多个模块中共享和使用一个RAM模块? [英] How can I share and use just one RAM module in multiple modules?

问题描述

我想在RAM中写入一个模块，然后从同一模块中读取到另一个模块中.我怎样才能做到这一点?我认为必须有一种通过引用其他模块来传递RAM模块的方法.例如:

I want to write a module in RAM and then read from the same into another module. How can I do this? I think there must be a way to pass RAM modules by referencing to other modules. For example:

在模块A中:

// write in ram and pass to module B

ram ram_ins();
ram_ins.wr_en = 1;
ram_ins.addr = 1;
ram_ins.data_in = 1234;
B b_ins(ram_ins); // pass by reference the ram_ins to the module B 

在模块B中:

// read from ram 

ram_ins.addr = 1;
reg [7:0] a;
assign a = ram_ins.data_out

模块B中的寄存器a必须为1234，因为在模块A中1234被写入RAM的地址1.

Register a in module B must be 1234, because in module A 1234 is written in address 1 of RAM.

推荐答案

您可以从需要此控制总线或通讯总线的其他模块的其他模块访问RAM.例如，Altera UFM I2C接口. RAM可以由模块A写入，并可以由模块B以不同的时钟读取(双端口RAM):

You can access to RAM from other modules you need some control module for this or communication bus. For example Altera UFM I2C interface. RAM can be write by module A and read by module B with different clocks (Dual-ported RAM):

http://www.asic-world.com/examples/verilog/ram_dp_sr_sw.html

http://www.asic-world.com/examples/verilog/ram_dp_ar_aw.html

在某种抽象级别上，I2C设备地址是您的参考.

At a certain level of abstraction I2C device address is your reference.

对不起，我的英语.

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