相当于Verilog的VHDL @(posedge clk) [英] VHDL equivalent for Verilog @(posedge clk)

问题描述

我对verilog不熟悉.我尽力尝试将其转换.

I am not familiar with verilog. I did my best trying to convert it.

在模拟时钟从'0'到'x'时，这很奇怪. 我怀疑这是问题

While simulating the clock is going from '0' to 'x' which is weird. I am suspecting this part to be the problem

repeat(9) @(posedge clk);
   DataIn_i <= 1'b1;
   DataIn_q <= 1'b1;
@(posedge clk);
  FillSel <= 1'b0;
  DataIn_i <= 1'b0;
  DataIn_q <= 1'b0;

这是指向两个工作台的链接.

here are links to both benches.

Verilog工作台- http://a.pomf.se/fvamqd.v Vhdl工作台- http://a.pomf.se/riolvf.vhd

Verilog bench - http://a.pomf.se/fvamqd.v Vhdl bench - http://a.pomf.se/riolvf.vhd

欢迎任何输入，谢谢.

谁能解释上面给出的Verilog代码?

Can anyone please explain the verilog code given above?

推荐答案

将Verilog的@posedge clk)转换为VHDL取决于其在Always块或初始块中的位置.如果这是该块的第一个构造，则可以

Translating Verilog's @posedge clk) to VHDL depends on where it is located in an always or initial block. If it's the very first construct of the block, you can do

Verilog:

always @(posedge signal)
begin
...
end

VHDL:

process(signal)
begin
  if rising_edge(signal) then  -- Older VHDL if (signal'event and signal = '1')
  ...
  end if;
end process;

当嵌入到块中时，使用wait until语句:

When embedded in the block, use the wait until statement:

Verilog: @(posedge clk);
VHDL:    wait until rising_edge(signal);

Verilog:  forever ...
VHDL:     loop ... end loop

Verilog: repeat(n) ...
VHDL:    for i in 1 to n loop ... end loop;

请注意，当我为Verilog编写...时，即表示后面的单个语句，或者后面的单个begin/end块.

Note that when I write ... for Verilog, that is for the single statement that follows, or a single begin/end block that follows.

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