是否有理由在VHDL和Verilog中初始化(不重置)信号? [英] Is there a reason to initialize (not reset) signals in VHDL and Verilog?
问题描述
我从未初始化过信号.这样，任何缺少复位或分配的信号将是未知的或初始化的.在某些参考代码中，它们具有初始化.这违背了我的愿望.另外，由于初始化无法合成，因此可能存在模拟/合成不匹配的情况.
I have never initialized signals. That way any signal missing a reset or assignment would be unknown or initialized. In some reference code they have initialization. This defeats what I wish. Also since intialization isn't synthesizable, there could be a simulation/synthesis mismatch.
在这种情况下，是否有任何理由初始化信号?
Is there any reason to initialize signals in this case?
编辑6/17/11:正如@ Adam12所问，这既适用于存储(Verilog reg)又适用于组合(有线)元素.
EDIT 6/17/11: As @Adam12 asked, this is for both storage (Verilog reg) and combinatorial (wire) elements.
推荐答案
(以下建议很大程度上取决于设备架构和综合工具，我是从Xilinx FPGA的经验(如Virtex-5部件)中得出的.)
(The following advice depends greatly on device architecture and synthesis tools, I speak from experience with Xilinx FPGAs such as Virtex-5 parts).
您关于初始化不可综合的假设是不正确的. 完全初始化信号是可以合成的！
Your supposition that initialization is not synthesizable is incorrect. Initializing a signal absolutely is synthesizable!
例如，可以将其合成，以便使用初始值对设备进行编程:
For example, this can be synthesized so it programs the device with an initial value:
signal arb_onebit : std_logic := '0';
signal arb_priority : std_logic_vector(3 downto 0) := "1011"
此外，您可以使用信号初始化并放弃传统的异步或同步全局重置方案来获得更好的结果质量(QoR).这是因为工具不再需要将重置信号路由到零件周围的所有FF.尽管某些较早的FPGA可能具有专用的复位资源，但在较新的器件中却并非如此.这意味着重置的路由方式与设计中的所有其他信号一样，从而减慢了构建过程并降低了性能.
Additionally, you can achieve better Quality of Results (QoR) using initialization of signals and forgoing the traditional async or sync global reset schemes. This is because the tools no longer need to route reset signals to all your FFs around your part. While some older generation FPGAs might have had dedicated resources for resets, this is not the case in newer parts. This means that the resets are routed just like every other signal in your design, slowing down your build process and dragging down performance.
您可以做什么?使用信号初始化.
What you can do instead? Use signal initialization.
- 使用专用的"GSR"(我相信是全局设置/重置).可通过专用的Xilinx原语进行访问.请注意，使用GSR时，不会重置设备的所有存储元件.例如，BRAM保留了我相信的值，但是FF被重置为初始化值.
- 对您的设备进行配置.这将导致整个设备从原始位流(位于PROM中)进行重新编程.每次从PROM加载设备时，所有存储元件(FF，BRAM等)都将进入初始化状态所要求的已知状态.如果您不初始化，我相信它默认为"0"状态.您可以使用FPGA编辑器(作为Xilinx工具集的一部分提供)之类的工具查看结果，从而验证存储元素被初始化为的状态
如果您真的只需要重置设计的一小部分(本地"重置)，则应按照通常处理重置的方式进行处理.
If you really need to reset just a small part of your design (a "local" reset) then you should handle this as you typically handle resets.
以下是有关Xilinx工具的一些参考资料:
Here are some references for Xilinx tools:
- 白皮书介绍了有关重置的高级注意事项
- XST 13.1用户指南参见第50和128页
- Xilinx Virtex 5 YouTube培训系列.第4部分看起来像您想要的.
- White paper describing high level considerations for resets
- XST 13.1 User Guide See page 50 and 128
- Xilinx Virtex 5 YouTube training series. Part 4 looks like what you want.
编辑
经过一些进一步的研究，我发现指定初始值虽然在某些情况下有助于改善QoR，但在其他情况下却可能会损害它.这实际上归结为您的综合工具供应商将如何兑现初始价值.从本质上讲，初始值是对工具的约束.当您的设计被合成并映射到零件时，便会在设计中添加一条注释:当您实现此存储元素时，请为其提供初始值."在许多情况下，添加此约束会阻碍元素的优化(删除，组合等).
After some further research I have found that specifying initial values, while helpful in improving QoR in some cases, it can hurt it in others. It really boils down to how your synthesis tool vendor will honor the initial value. At its core, an initial value is a constraint on the tool. When your design is synthesized and then mapped to the part, a note gets added to your design that "when you implement this memory element, give it this initial value." In many cases, adding this constraint prevents the element from being optimized (removed, combined, etc).
建议:对于重置和初始化，没有硬性/快速性/一应俱全的规则.为了获得最佳的优化和资源利用，您必须知道您的综合工具，并且必须知道您的目标技术.
Suggestion: There is no hard/fast/one-size-fits-all rule for reset and initialization. For best optimization and resource utilization you must know your synthesis tool, and you must know your targeted technology.
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