“其他处理器以一致的顺序看到两个存储区"是什么意思? [英] What does it mean that "two store are seen in a consistent order by other processors"?

问题描述

在英特尔手册中:

部分:"8.2.2 P6和更新的处理器家族中的存储器顺序"

section of : "8.2.2 Memory Ordering in P6 and More Recent Processor Families"

除了执行存储的处理器之外，处理器会以一致的顺序查看任何两个存储

Any two stores are seen in a consistent order by processors other than those performing the stores

此声明的含义是什么?

推荐答案

这意味着没有IRIW重新排序(独立读者，独立作家；至少4个独立的核心，每个作者和读者至少2个). 2位读者将永远同意在其他2个商店中执行其他核心的顺序.

It means no IRIW reordering (Independent Readers, Independent Writers; at least 4 separate cores, at least 2 each writers and readers). 2 readers will always agree on the order of any 2 stores performed other cores.

较弱的内存模型不不能保证这一点，例如ISO C ++ 11仅对seq_cst操作而不是acq_rel或任何较弱的阶数保证它.

Weaker memory models don't guarantee this, for example ISO C++11 only guarantees it for seq_cst operations, not for acq_rel or any weaker orders.

一些硬件内存模型允许在纸上使用它，包括ARMv8之前的ARM.但是实际上，这是非常罕见的，POWER硬件实际上可以在实践中违反此规定:请参阅我的回答

A few hardware memory models allow it on paper, including ARM before ARMv8. But in practice it's very rare POWER hardware can actually violate this in practice: See my answer Will two atomic writes to different locations in different threads always be seen in the same order by other threads? for an explanation of a hardware mechanism that can make it happen (store-forwarding between SMT "hyperthreads" on the same physical core making a store visible to some cores before it's globally visible).

x86禁止这种情况，因此超线程之间的通信必须等待提交到L1d缓存，即在其他 any 之前等待存储在全局可见(感谢MESI).核心可以看到它. 会发生什么用于线程之间的数据交换，这些线程是否正在使用HT在一个Core上执行?

x86 forbids this so communication between hyperthreads has to wait for commit to L1d cache, i.e. waiting for the store to be globally visible (thanks to MESI) before any other core can see it. What will be used for data exchange between threads are executing on one Core with HT?

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