并发商店以一致的顺序显示 [英] Concurrent stores seen in a consistent order

问题描述

英特尔架构软件开发人员手册， 2012年8月，第1卷。 3A，Sect。 8.2.2：

The Intel Architectures Software Developer's Manual, Aug. 2012, vol. 3A, sect. 8.2.2:

任何两个商店都是由执行商店的
以外的处理商以一致的顺序看到的。 p>

Any two stores are seen in a consistent order by processors other than those performing the stores.

但是这样可以吗？

我问的原因是：具有超线程的双核Intel i7处理器。根据手册 1。在图2-8中，i7的逻辑处理器0和1共享L1 / L2高速缓存，但是其逻辑处理器2和3共享不同的L1 / L2高速缓存，而所有逻辑处理器共享单个L3高速缓存。假设不共享L1 / L2高速缓存的逻辑处理器0和2在大约相同的时间写入相同的存储器位置，并且该写入暂时不深于L2。逻辑处理器1和3（它们是执行商店的处理器之外的处理器）然后看到两个商店以不一致的顺序吗？

The reason I ask is this: Consider a dual-core Intel i7 processor with HyperThreading. According to the Manual's vol. 1, Fig. 2-8, the i7's logical processors 0 and 1 share an L1/L2 cache, but its logical processors 2 and 3 share a different L1/L2 cache -- whereas all the logical processors share a single L3 cache. Suppose that logical processors 0 and 2 -- which do not share an L1/L2 cache -- write to the same memory location at about the same time, and that the writes go no deeper than L2 for the moment. Could not logical processors 1 and 3 (which are "processors other than those performing the stores") then see the "two stores in an inconsistent order"?

，逻辑处理器0和2不能发出SFENCE指令，而逻辑处理器1和3发出LFENCE指令？尽管如此，手册似乎并非如此，它在这个问题上的意见并不只是一个误印。它看起来故意。我很困惑。

To achieve consistency, must not logical processors 0 and 2 issue SFENCE instructions, and logical processors 1 and 3 issue LFENCE instructions? Notwithstanding, the Manual seems to think otherwise, and its opinion in the matter does not have the look of a mere misprint. It looks deliberate. I'm confused.

UPDATE

根据@ Benoit的回答，一个以下问题：L1和L2的唯一目的是加速负载。它是L3加速商店。是这样吗？

In light of @Benoit's answer, a following question: The only purpose of L1 and L2 therefore is to speed loads. It is L3 that speeds stores. Is that right?

推荐答案

这是一个棘手的问题！但我会尝试...

Ouch, this is a tough question! But I'll try...

写入不深于L2

the writes go no deeper than L2

基本上这是不可能的，因为Intel使用包含缓存。任何写入L1的数据也将在L2和L3中发生，除非通过CR0 / MTRR禁止缓存来防止缓存。

Basically this is impossible since Intel uses inclusive caches. Any data written to L1, will also takes place in L2 and L3, unless you prevent from caching by disabling them through CR0/MTRR.

是仲裁机制：处理器发出写入数据的请求，并且仲裁器从来自每个请求队列的挂起的请求中选择授予了哪个请求。所选择的请求被广播到窥探者，然后被广播到高速缓存。我想这将防止竞赛，强制执行请求的人以外的处理器看到的一致性顺序。

That being said, I guess there are arbitration mechanisms: processors issue a request to write data and an arbiter selects which request is granted from among the pending requests from each of the request queues. The selected requests are broadcasted to the snoopers, and to caches then. I suppose it would prevent from race, enforcing the consistent order seen by processors other than the one performing the request.

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