在x86顺序一致原子负荷 [英] sequentially-consistent atomic load on x86

问题描述

我感兴趣的是在x86顺序一致负荷运转。据我看到汇编程序，由编译器生成的，因为我知道保证具有获取语义是尽可能实现为在x86普通负载，但是普通的负载，而普通店都保证有发布。顺序一致的店面被实现为锁定XCHG，而负载为纯负荷。这听起来很奇怪，我，请你详细解释一下吗？

I'm interested in sequentially-consistent load operation on x86. As far as I see from assembler listing, generated by compiler it is implemented as a plain load on x86, however plain loads as far as I know guaranteed to have acquire semantics, while plain stores are guaranteed to have release. Sequentially-consistent store is implemented as locked xchg, while load as plain load. That sounds strange to me, could you please explain this in details?

添加

在互联网刚刚发现，即按顺序一致原子负荷可只要存储与锁定XCHG所做的一切一样简单MOV，但没有证明和文档没有任何联系。你知道我在哪里可以阅读有关？

Just found in internet, that sequentially-consistent atomic load could be done as simple mov as long as store is done with locked xchg, but there was no prove and no links to documentation. Do you know where can I read about that?

先谢谢了。

推荐答案

一个普通的 MOV x86上是足够的原子顺序一致的负载，只要SC商店与锁定 ED指令，值正确对齐，并且使用正常WB缓存模式完成。

A plain MOV on x86 is sufficient for an atomic sequentially consistent load, as long as SC stores are done with LOCKed instructions, the value is correctly aligned, and "normal" WB cache mode is used.

请参阅我的博客文章<一个href=\"http://www.justsoftwaresolutions.co.uk/threading/intel-memory-ordering-and-c++-memory-model.html\">http://www.justsoftwaresolutions.co.uk/threading/intel-memory-ordering-and-c++-memory-model.html为全面映射，并在<一个英特尔处理器文档href=\"http://developer.intel.com/products/processor/manuals/index.htm\">http://developer.intel.com/products/processor/manuals/index.htm对于允许的序的细节。

See my blog post at http://www.justsoftwaresolutions.co.uk/threading/intel-memory-ordering-and-c++-memory-model.html for the full mapping, and the Intel processor docs at http://developer.intel.com/products/processor/manuals/index.htm for the details of the allowed orderings.

如果您使用WC缓存模式或非时间的指示，如 MOVNTI 则全盘皆输，因为处理器并不一定写入数据回及时的主存储器。

If you use "WC" cache mode or "non-temporal" instructions such as MOVNTI then all bets are off, as the processor doesn't necessarily write the data back to main memory in a timely manner.

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