在MIPS的HI和LO寄存器存储值 [英] Storing values in HI and LO registers of MIPS

问题描述

我写在MIPS某些code和我来那里的要求是存储结果，暂时在 HI 和<点code> LO 特殊寄存器（均为8个字节宽）。这些指令是在我手上：

I am writing certain code in MIPS and I've come to the point where the requirement is to store the result, temporarily, in HI and LO special registers (both are 8 bytes wide). These instructions are at my disposal:

divu     s,t 	lo <-- s div t ; hi <-- s mod t
multu    s,t 	hi / lo < -- s * t ;

因此​​， DIVU 专卖店在 LO在 HI <剩余和/分工导致code>，而 multu 保存乘法导致 LO （下8个字节）和 HI （高8个字节）。

So, divu stores result of division in LO and remainder in HI, while multu stores result of multiplication in LO (lower 8 bytes) and HI (higher 8 bytes).

后来，检索 HI结果和 LO 寄存器，我可以：

Later, to retrieve result from HI and LO registers, I can:

mfhi $v0
mflo $v1

我已经想出如何计算的结果保存在 LO ：

ori     $v0,$0,1            # Store result from $a0 into LO
divu    $a0,$v0

• 在 DIVU 专卖店在LO分工造成的，所以我只是除以1的结果得到它。


• the divu stores result of the division in LO, so I just divide result by 1 to get it there.

然而，存储 HI 更复杂。一种方法是强制 multu 指令通过32位（8字节）的值偏移：

However, storing in HI is more complicated. One way would be to force multu instruction to shift the value by 32 bits (8 bytes):

multu    $a0,0x80000000     # Shift $a0 by 32 bits and store into HI/LO

但是，其结果是，在 HI值是的，它应该是1位权（所以如果我值为 0100 1000 然后 HI 将包含 0010 0100 ）。

But, the result is that the value in HI is 1 bit right of where it should be (so if my value is 0100 1000 then HI will contain 0010 0100).

有谁知道如何保存的东西在 HI 注册？

Does anyone know how to store something in HI register?

推荐答案

我想延长尼尔斯Pipenbrinck答案：

I'd like to extend Nils Pipenbrinck answer:

从MIPS32 arquitechture程序员

From MIPS32 arquitechture for programmers

格式：MIPS32（MIPS I）

Format: MIPS32 (MIPS I)

  MTHI rs

用途：
要将GPR复制到专用寄存器HI

Purpose: To copy a GPR to the special purpose HI register

Description: HI ← rs

GPR Rs的内容被装入特殊寄存器HI。

The contents of GPR rs are loaded into special register HI.

限制：

写入HI / LO对由DIV，DIVU，MULT，或MULTU一个计算的结果必须由MFHI或MFLO阅读
一个新的结果之前，可写入或高或低。
如果一个MTHI指令被执行以下这些算术指令的一个，而是MFLO或MFHI之前
指令，LO的内容是联合国preDICTABLE。下面的例子显示了这种非法的情况：

A computed result written to the HI/LO pair by DIV, DIVU,MULT, or MULTU must be read by MFHI or MFLO before a new result can be written into either HI or LO. If an MTHI instruction is executed following one of these arithmetic instructions, but before an MFLO or MFHI instruction, the contents of LO are UNPREDICTABLE. The following example shows this illegal situation:

 MUL       r2,r4   # start operation that will eventually write to HI,LO
 ...               # code not containing mfhi or mflo
 MTHI      r6
 ...               # code not containing mflo
                   # this mflo would get an UNPREDICTABLE value
 MFLO      r3

历史资讯：

在MIPS I-III，如果其中两个preceding指令是MFHI，即MFHI的结果是联合国preDICTABLE。
该HI的读取或LO特殊寄存器必须从两个写信给他们任何后续指令分开
或更多指令。在MIPS IV及更高版本，包括MIPS32和MIPS64，此限制不存在。

In MIPS I-III, if either of the two preceding instructions is MF the result of that MFHI is UNPREDICTABLE. Reads of the HI or LO special register must be separated from any subsequent instructions that write to them by two or more instructions. In MIPS IV and later, including MIPS32 and MIPS64, this restriction does not exist.

格式：MIPS32（MIPS I）

Format: MIPS32 (MIPS I)

    MTLO rs

用途：
要将GPR复制到专用寄存器LO
说明：

Purpose: To copy a GPR to the special purpose LO register Description:

 LO ← rs

GPR Rs的内容被装入特殊寄存器LO。

The contents of GPR rs are loaded into special register LO.

限制：
写到HI / LO对由DIV，DIVU，MULT，或MULTU一个计算结果必须由MFHI或MFLO一个新的结果之前，读取可写入无论是高或低。

Restrictions: A computed result written to the HI/LO pair by DIV, DIVU, MULT, or MULTU must be read by MFHI or MFLO before a new result can be written into either HI or LO.

如果以下的这些算术指令之一执行一个MTLO指令，而是一个MFLO或MFHI指令之前，HI的内容是联合国preDICTABLE。
 下面的例子显示了这种非法的情况：

If an MTLO instruction is executed following one of these arithmetic instructions, but before an MFLO or MFHI instruction, the contents of HI are UNPREDICTABLE. The following example shows this illegal situation:

 MUL       r2,r4   # start operation that will eventually write to HI,LO
 ...               # code not containing mfhi or mflo
 MTLO      r6
 ...               # code not containing mfhi
                   # this mfhi would get an UNPREDICTABLE value
 MFHI      r3

历史资讯：

在MIPS I-III，如果其中两个preceding指令是MFHI，即MFHI的结果是联合国preDICTABLE。
该HI的读取或LO特殊寄存器必须从两个写信给他们任何后续指令分开
或更多指令。在MIPS IV及更高版本，包括MIPS32和MIPS64，此限制不存在。

In MIPS I-III, if either of the two preceding instructions is MF the result of that MFHI is UNPREDICTABLE. Reads of the HI or LO special register must be separated from any subsequent instructions that write to them by two or more instructions. In MIPS IV and later, including MIPS32 and MIPS64, this restriction does not exist.

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