避免CortexM中断嵌套 [英] Avoiding CortexM Interrupt Nesting

问题描述

我想避免在基于CortexM的微控制器的中断入口处嵌套中断.

I want to avoid nested interrupts at the interrupts entry in a CortexM based microcontroller.

要实现此目的，我有一个包含中断向量的汇编文件，每个向量的第一条指令是全局禁用中断的指令(CPSID I). 在每个单独的中断处理程序(用C编写)之后，执行返回到公共汇编例程，该例程使用指令CPSIE I重新启用中断，并使用指令BX LR触发从中断/异常过程返回.

To achieve this I have an assembly file containing interrupt vectors and first instruction of each vector is the instruction (CPSID I) to disable interrupts globally. After every individual interrupt handler(written in C), execution returns to a common assembly routine which re-enables the interrupts with instruction CPSIE I and return from Interrupt/Exception process is triggered with instruction BX LR.

在中断入口处，CortexM会自动堆叠包含易失性上下文(调用方保存的上下文)的异常帧，并跳转到异常/中断向量的第一条指令.

On interrupt entry CortexM auto-stacks the exception frame, containing volatile context (Caller saved context) and jumps to the first instruction of the exception/interrupt vector.

根据 ARM信息居中至少需要12个周期才能完成堆栈过程并从NVIC(嵌套矢量中断控制器)中提取目标向量的第一条指令的地址.如果在堆叠过程中又有一个更高优先级的中断到达(这是延迟到达"的情况)，则将继续堆叠过程，但将首先为更高优先级的进程提供服务.

According to ARM Info Center it takes at least 12 cycles to complete the stacking process and fetching of the address of the first instruction of target vector from NVIC (Nested Vectored Interrupt Controller). If another higher priority interrupt arrives during the stacking process(It is a Late arrival case), stacking process is continued but the higher priority process will be serviced first.

我的第一个问题是，是否将这种迟到情况视为嵌套中断方案，即LR寄存器将是0xFFFF FFF1(仅考虑基本帧)?

My first question is, is this Late Arrival case considered as nested interrupt scenario i.e the LR register will be 0xFFFF FFF1 (Considering Basic Frame only)?

第二，是否有可能在完成堆叠过程和执行beofre CPSID I之间接受异常?

Second, Is it possible that an exception can be accepted between the stacking process is completed and beofre CPSID I gets executed?

推荐答案

避免嵌套的简单方法是使所有中断都具有相同的优先级.

The simple way to avoid nesting would be to have all interrupts at the same priority.

如果愿意，您仍然可以使用子优先级对它们进行优先级排序，但是我不确定这会给您带来任何好处.

You could still prioritise them using sub-priorities if you like but I am not sure this would give you any benefit.

延迟到达有点像嵌套，只是较高优先级的中断将在较低优先级的中断之前运行.优先级较低的中断会拖到优先级较高的中断上.

Late arrival is a bit like nesting, except the higher priority interrupt will run before the lower priority interrupt. The lower priority interrupt will tail chain onto the higher priority interrupt.

是的，可以在执行CPSID I之前接受更高优先级的中断.根据时间的不同，您可能会遇到延迟到达或嵌套的情况.

Yes it is possible for a higher priority interrupt to be accepted before you execute CPSID I. Depending on the timing you would either get a late arrival or nesting scenario.

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