乱序执行会导致推测性的内存访问吗? [英] Can out-of-order execution lead to speculative memory accesses?

问题描述

乱序处理器遇到类似情况

When a out-of-order processor encounters something like

LOAD R1, 0x1337
LOAD R2, $R1
LOAD R3, 0x42

假设所有访问都将导致高速缓存未命中，那么处理器可以在向内存控制器询问$ R1甚至0x1337的内容之前向存储器控制器询问0x42的内容吗?如果是这样，假设访问$ R1会导致异常(例如分段错误)，我们可以认为0x42是推测加载的，对吗?

Assuming that all accesses will result in a cache miss, can the processor ask the memory controller for the contents of 0x42 before the it asks for the content of $R1 or even 0x1337? If so, assuming that accessing $R1 will result in a exception (e.g., segmentation fault), we can consider that 0x42 was loaded speculatively, correct?

顺便说一句，当加载存储单元向存储控制器发送请求时，它可以在收到前一个请求的答案之前发送第二个请求吗?

And by the way, when a load-store unit sends a request to the memory controller, can it send a second request before receiving the answer to the previous one?

我的问题并不特别针对任何体系结构.欢迎回答与任何主流架构有关的问题.

My question doesn't target any architecture in particular. Answers related to any mainstream architecture are welcomed.

推荐答案

问题的答案取决于CPU的内存排序模型，该模型与允许乱序执行的CPU不同.如果CPU实现了商店总计订购(例如x86或Sparc)，那么您的问题的答案是0x42将不会在0x1337之前加载

Answer to your question depends on the memory ordering model of your CPU, which is not the same as the CPU allowing out of order execution. If the CPU implements Total store ordering (eg x86 or Sparc) then the answer to your question is 0x42 will not be loaded before 0x1337

如果cpu实现了宽松的内存模型(例如IA-64，PowerPC，alpha)，则在没有内存围栏指令的情况下，所有赌注都将被取消，因为它将首先被访问.除非您正在执行IO或处理多线程代码，否则这应该无关紧要.

If the cpu implements a relaxed memory model (eg IA-64, PowerPC, alpha), then in the absence of a memory fence instruction all bets are off as to which will be accessed first. This should be of little relevance unless you are doing IO, or dealing with multi-threaded code.

您应注意，某些CPU(例如Itanium)确实具有宽松的内存模型(因此读取可能是乱序的)，但没有任何乱序的执行逻辑，因为它们希望编译器在其中对指令和推测性指令进行排序.而不是在OOE上花费硅空间的最佳方式

you should note that some CPU's (eg Itanium) do have relaxed memory models (so reads may be out of order) but do NOT have any out of order execution logic since they expect the compiler to order the instructions and speculative instructions in an optimal way rather than spend silicon space on OOE

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