乱序执行和内存的栅栏 [英] Out of Order Execution and Memory Fences

问题描述

我知道，现代的CPU可以执行乱序，但是他们总是退有序的结果，如维基百科描述。

I know that modern CPUs can execute out of order, However they always retire the results in-order, as described by wikipedia.

走出奥德处理器填补这些时间与准备其他指令，，然后重新整理插槽末的结果，使之出现的指令进行处理正常。

"Out of Oder processors fill these "slots" in time with other instructions that are ready, then re-order the results at the end to make it appear that the instructions were processed as normal."

现在内存围栏，据说使用多核平台的时候是必须的，因为由于乱序执行，错误的价值的 X 在这里可以打印出来。

Now memory fences are said to be required when using multicore platforms, because owing to Out of Order execution, wrong value of x can be printed here.

Processor #1:
 while f == 0
  ;
 print x; // x might not be 42 here

Processor #2:
 x = 42;
 // Memory fence required here
 f = 1

现在我的问题是，既然乱序处理器（在多核处理器的情况下，核心我认为）永远退休结果有序，那么什么是内存栅栏的必要性。不要在多核处理器的内核看到的结果与其他核退役唯一或他们也看到成果，这是飞行？

Now my question is, since Out of Order Processors (Cores in case of MultiCore Processors I assume) always retire the results In-Order, then what is the necessity of Memory fences. Don't the cores of a multicore processor sees results retired from other cores only or they also see results which are in-flight?

我的意思是比如我上面给了，当处理器2将最终退役的结果，结果的 X 应来之前的˚F，对不对？我知道，乱序执行过程中它可能已修改的˚F之前的 X ，但它必须在还没有退役的它的 X ，对不对？

I mean in the example I gave above, when Processor 2 will eventually retire the results, the result of x should come before f, right? I know that during out of order execution it might have modified f before x but it must have not retired it before x, right?

现在配有秩序退休结果和地方高速缓存一致性的机制，为什么你需要存储在围栏86？

Now with In-Order retiring of results and cache coherence mechanism in place, why would you ever need memory fences in x86?

推荐答案

本教程介绍的问题：<一href=\"http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-95-7.pdf\">http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-95-7.pdf

FWIW，其中存储顺序问题发生在现代的x86处理器，其原因是，虽然86内存一致性模型提供了相当强的一致性，需要明确的障碍来处理读后写的一致性。这是因为一种叫做存储缓冲区。

FWIW, where memory ordering issues happen on modern x86 processors, the reason is that while the x86 memory consistency model offers quite strong consistency, explicit barriers are needed to handle read-after-write consistency. This is due to something called the "store buffer".

也就是说，86是顺序一致（好和容易推理），除了负载可能会重新排序WRT更早商店。也就是说，如果处理器执行该序列

That is, x86 is sequentially consistent (nice and easy to reason about) except that loads may be reordered wrt earlier stores. That is, if the processor executes the sequence

store x
load y

，则处理器总线上，这可能被视为

then on the processor bus this may be seen as

load y
store x

这样做的原因行为是前面提到的存储缓冲区，这是写一个小缓冲区，他们走出去的系统总线之前。加载延迟，OTOH，为性能的一个关键问题，因此负载被允许插队。

The reason for this behavior is the afore-mentioned store buffer, which is a small buffer for writes before they go out on the system bus. Load latency is, OTOH, a critical issue for performance, and hence loads are permitted to "jump the queue".

见8.2 <一个href=\"http://download.intel.com/design/processor/manuals/253668.pdf\">http://download.intel.com/design/processor/manuals/253668.pdf

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