的pthread_mutex_lock是否包含内存栅栏指令？ [英] Does pthread_mutex_lock contains memory fence instruction?

问题描述

不要的pthread_mutex_lock 和调用pthread_mutex_unlock 函数调用的存储栅栏/屏障指令？或做喜欢的低级说明 compare_and_swap 含蓄有记忆障碍是什么？

Do pthread_mutex_lock and pthread_mutex_unlock functions call memory fence/barrier instructions? Or do the the lower level instructions like compare_and_swap implicity have memory barriers?

推荐答案

请看一看部分的 4.11 的POSIX规范的。

Please take a look at section 4.11 of the POSIX specification.

应用应确保通过控制一个以上的线程访问任何存储器位置（线程或进程）被限制，使得没有控制线程能够读取或修改的存储器位置，而控制的另一个线程可以修改它。这样的访问是使用同步线程执行并同步也相对于其他线程记忆功能的限制。 [重点煤矿]

Applications shall ensure that access to any memory location by more than one thread of control (threads or processes) is restricted such that no thread of control can read or modify a memory location while another thread of control may be modifying it. Such access is restricted using functions that synchronize thread execution and also synchronize memory with respect to other threads. [emphasis mine]

然后给出一个函数列表，其中同步内存，再加上一些额外的注意事项。

Then a list of functions is given which synchronize memory, plus a few additional notes.

如果需要一些架构内存屏障指令，那么这些必须被使用。

If that requires memory barrier instructions on some architecture, then those must be used.

关于 compare_and_swap ：这是不是在POSIX;检查无论你正在使用的文件。例如，IBM <一href=\"http://www-01.ibm.com/support/knowledgecenter/ssw_aix_53/com.ibm.aix.basetechref/doc/basetrf1/compare_and_swap.htm%23yhyji20dthom?lang=en\">defines 。一个 compare_and_swap 功能为AIX 5.3 它不具有完全的内存屏障语义的文档注云：

About compare_and_swap: that isn't in POSIX; check the documentation for whatever you are using. For instance, IBM defines a compare_and_swap function for AIX 5.3. which doesn't have full memory barrier semantics The documentation note says:

如果compare_and_swap用作锁定原语，在任何关键部分的开始插入的iSync。

If compare_and_swap is used as a locking primitive, insert an isync at the start of any critical sections.

从这个文件，我们可以猜测，IBM的 compare_and_swap 有语义的释放：因为文档不要求关键节结束的一个障碍。收购处理器需要发出的iSync，以确保它不读书陈旧的数据，但出版处理器不必做任何事情。

From this documentation we can guess that IBM's compare_and_swap has release semantics: since the documentation does not require a barrier for the end of the critical section. The acquiring processor needs to issue an isync to make sure it is not reading stale data, but the publishing processor doesn't have to do anything.

在指令级，一些处理器已经比较和一定的同步保证交换，有的则没有。

At the instruction level, some processors have compare and swap with certain synchronizing guarantees, and some don't.

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