如何在Verilog中将二维数组中的所有位设置为0? [英] How to set all the bits to be 0 in a two-dimensional array in Verilog?

问题描述

我建立了一个8 * 2bits数组来表示Verilog中的一块内存

I've built a 8*2bits array to represent a piece of memory in Verilog

reg [1:0] m [0:7]

此存储器有一个复位信号，如果reset为1，则该存储器中的所有位都应复位为0.但是我不知道如何以一种简洁的方式设置m的所有位，因为如果内存中有成千上万的位，以下方法显然是不可行的.

There is a reset signal for this memory and if reset is 1, all the bits in this memory should be reset to 0. But I don't know how to set all the bits of m in a concise way, because if there are hundreds thousands of bits in the memory, the following way is obviously unfeasible.

always@(posedge clk or posedge reset)
begin
  if (reset) 
    begin
      m[0]<=2'b00;
      m[1]<=2'b00;
      m[2]<=2'b00;
      m[3]<=2'b00;        
      m[4]<=2'b00;
      m[5]<=2'b00;
      m[6]<=2'b00;
      m[7]<=2'b00;
    end
  else
    ....
end

推荐答案

使用 for 循环:

  integer i;
  always@(posedge clk or posedge reset)
  begin
    if (reset) 
      begin
        for (i=0; i<8; i=i+1) m[i] <= 2'b00;
      end
    else
      ....
  end

IEEE Std 1800-2012 中对此进行了描述(例如，第12.7.1节for循环).

This is described in the IEEE Std 1800-2012 (Section 12.7.1 The for-loop, for example).

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