在嵌套的If-Else语句(VHDL)中推断锁存器 [英] Inferring Latch in a nested If-Else statement (VHDL)

问题描述

我的代码推断出一个闩锁，我遇到了问题.我知道闩锁通常是由于没有考虑到输出的所有情况造成的，但是在这种情况下，我还没有看到任何在线案例可以解决这一问题.我在流程语句中有一个嵌套的if-else语句，如下所示.只是为了快速解释我在做什么，在启动重置后，reset_cnt将变高并启动一个计数过程，以进行最多24个周期的sck并重复其自身，并且输出将递增.

I have a problem with an inferred latch with my code. I know a latch is usually caused by not having all situations for an output accounted for, but in this situation, I haven't seen any online examples that cover this. I have a nested if-else statement in a process statement as shown below. Just to quickly explain what I'm doing, after a reset is initiated, reset_cnt will go high and initiate a counting process for sck up to 24 cycles and repeat itself and output will increment.

clock_counter: process(reset, sck, counter, output, reset_cnt, reset_done)
begin
  if (reset = '1') then
    counter <= 0;
    output <= 1;
    reset_cnt <= 1;
    reset_done <= '1';
  else
    reset_done <= '1';   -- added to fix
    reset_cnt <= 1;      -- added to fix
    output <= output;          -- added to fix (didn't work)
    if (reset_cnt AND counter = 24) then
      counter <= 0;
      output <= output + 1;
    elsif (rising_edge(sck)) then
      counter <= counter + 1;
    end if;
  end if;
end process;

最初，我遇到了3个闩锁的问题:reset_done，reset_cnt和输出.我添加了一些代码行(带有注释的代码行)，并且能够删除reset_done和reset_cnt的闩锁.看起来我仍然可以得到推断出的闩锁，因为我在嵌套的If语句中使用了它.我以为:

Originally I had a problem with 3 latches: reset_done, reset_cnt, and output. I added in some lines of code (the ones with the comments next to it) and I was able to remove latches for reset_done and reset_cnt. It looks like I still get an inferred latch for out because I use it in the nested If statement. I thought:

output <= output;

可能会工作，但我想不会.有人知道如何解决这种闩锁吗?我应该提到，我尝试将其拆分为2个流程语句，然后将其制成case语句，但这也不起作用.任何帮助或建议，我们将不胜感激！

might work, but I guess not. Does anyone know how to fix this kind of latch? I should mention, I've tried splitting this up into 2 process statements, and making it into a case statement, but that didn't work either. Any help or advice is much appreciated!

推荐答案

此代码是完全错误的.很难修复，因为它在一个过程中合并了多个错误.

This code is totally wrong. It's hard to fix because it combines multiple mistakes in one process.

我将尝试列举您的一些错误:

I'll try to enumerate some of your mistakes:

1. 敏感度列表不应使用 output 和 reset_done .
2. output< = output +1; 无法合成，否则将在仿真中创建无限循环
3. 您需要将组合逻辑和顺序逻辑分为两个过程
4. reset_done 和 reset_cnt 是无用的，因为它们始终为'1'
5. reset_cnt 是一个整数，不能与表达式 counter = 24
中的布尔值进行与"运算
6. 从不写 output< = output;

1. The sensitivity list should not use output and reset_done.
2. output <= output + 1; cannot be synthesized or will create an endless loop in simulation
3. you need to distinguish combinational and sequential logic into two processes
4. reset_done and reset_cnt are useless, because they are always '1'
5. reset_cnt is an integer, this cannot be ANDed with a boolean from expression counter = 24
6. never write output <= output;

我建议研究VHDL的组合和顺序过程以及编码模式.

I suggest to study about combinational and sequential processes as well as coding patterns for VHDL.

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