实施缓存建模框架 [英] Implementing a cache modeling framework
问题描述
我想缓存的Intel架构的行为（LRU，包容，K路关联，等等）的模式，我读过维基百科，乌尔里希Drepper的记忆非常好的论文，和Intel手册卷3A：系统编程指南（第11章，但它不是非常有帮助的，因为他们唯一的解释可以在软件层面上进行操作）。我也看到了一堆的学术论文，但像往常一样，他们不作可用于复制其code ...甚至要求后。我的问题是，是否有已经是公开可用的模型缓存行为框架？如果没有，是否有一个文档在最深层次英特尔详述缓存的行为？我无法找到一个。
I would like to model the behavior of caches in Intel architectures (LRU, inclusive, K-Way Associative, etc)., I've read wikipedia, Ulrich Drepper's great paper on memory, and the Intel Manual Volume 3A: System Programming Guide (chapter 11, but it's not very helpful, because they only explain what can be manipulated at the software level). I've also read a bunch of academic papers, but as usual, they do not make their code available for replication... even after asking for it. My question is, is there already a publicly available framework to model cache behavior? If not, is there a document detailing the behavior of caches from Intel at the deepest levels? I could not find one.
推荐答案
有大量的缓存模拟器在那里，的 DINERO 作为例如（双关语显然是）应该是相当简单，通常用于教育目的。结果
请注意，这个模拟器的跟踪驱动，这意味着饲料内存访问地址的列表，它不知道如何运行二进制。您可以通过使用二进制检测工具模仿他们产生这样的痕迹，例如为
There are plenty of cache simulators out there, Dinero for e.g. (pun obviously intended) should be fairly simple and is often used for educational purposes.
Note that this simulator is trace-driven, it means it feeds on a list of memory access addresses, it doesn't know how to run a binary. You can produce such traces by emulating them with binary instrumentation tools, for e.g.
等。注意，其中一些提供内部缓存模拟器已经，并且可能一起玩。
etc.. Note that some of these offer internal cache simulators already, and may be possible to play with.
其它模拟器可以模拟完整的CPU /系统行为，不只是缓存，因此能够支持运行的二进制。他们中的大多数包括在其中一个模拟缓存系统。对于例如：
Other simulators can simulate full CPU/system behavior, not just caches, and can therefore support running a binary. Most of them include within them a simulated cache system. For e.g.:
- 的 gem5 的
- 的 SimpleScalar的 的
- 的 multi2sim 的
- 的 marss86 的
和其他许多人
在另一方面，写你自己的缓存模拟器是相当简单的 - 如果你能在一个内存跟踪工作（写入实际fronend的方式更加复杂）。您将不能够获得英特尔/ AMD产品的实际缓存过于详细的规范，但基本功能详尽的任何计算机体系结构的教科书，甚至维基百科，参数（尺寸，相关性，一致性策略）大多是中记录发布的指南，可能经常代产品之间切换。您可以随时在这里问，如果你遇到的任何具体问题：）
On the other hand, writing your own cache simulator is fairly simple - if you can work on a memory trace (writing an actual fronend is way more complicated). You won't be able to get a too detailed spec on actual caches in Intel/AMD products, but the basic functionality is detailed in any computer architecture textbook or even wikipedia, the parameters (size, associativity, coherency policies) are mostly documented in the published guides, and may often change between product generations. You can always ask here if you encounter any specific question :)
至于问题的第二部分 - 有确切的缓存实现英特尔CPU的不公开提供的文档，但干燥的规格（大小，关联性，政策）都是在<一个href=\"http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf\"相对=nofollow>优化指南：
现在，造型这些缓存应该是简单的，但可能有一些隐藏的注意事项，如断电功能或专门的LRU行为。一个这样的例子报告可以在这里找到 - http://blog.stuffedcow.net / 2013/01 / IVB缓存替换/ （如果这是真的，它可能是值得实施精度），但除了我相信整体行为不应该被这些细节受到太多影响，对于任何实际用途。
Regarding the second part of the question - there's no publicly available documentation of the exact cache implementation of Intel CPUs, but the dry "specs" (size, associativity, policies) are in the optimization guide: Now, modeling these caches should be straightforward, but there may be some hidden caveats, like powerdown features or specialized LRU behaviors. One such reported example can be found here - http://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ (if this is true, it might be worth implementing for accuracy), but aside from that I believe the overall behavior shouldn't be affected by these details too much, for any practical use.
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