这是由于操作系统中的IRQ延迟？ [英] What is the irq latency due to the operating system?
问题描述
- 我怎么能估计在ARM处理器上的IRQ延迟？
- 什么是IRQ延迟的定义是什么？
推荐答案
垫和维迪奇将提供一些良好的信息中断延迟。有<击>两个是多了一个问题，我想补充，通过垫给三个。
Mats and Nemanja give some good information on interrupt latency. There are two is one more issue I would add, to the three given by Mats.
- 其他同步/几乎同时中断。
- 操作系统的延迟增加，由于屏蔽中断。 编辑：这是垫的答案，只是没有那么多的解释
- Other simultaneous/near simultaneous interrupts.
- OS latency added due to masking interrupts. This is in Mats answer, just not explained as much.
如果单核正在处理的中断，那么当发生多个中断时，同时，通常有一定的分辨率优先。然而，中断通常是在中断处理程序，除非优先级中断处理启用禁用。因此，例如，一个缓慢的NAND闪存的IRQ发信号并运行，然后发生以太网中断时，它可能被延迟，直到NAND闪存的IRQ完成。当然，如果你有先决中断和你所关心的NAND闪存中断，那么事情实际上，更糟糕如果以太网优先。
If a single core is processing interrupts, then when multiple interrupts occur at the same time, usually there is some resolution priority. However, interrupts are often disabled in the interrupt handler unless priority interrupt handling is enabled. So for example, a slow NAND flash IRQ is signaled and running and then an Ethernet interrupt occurs, it may be delayed until the NAND flash IRQ finishes. Of course, if you have priorty interrupts and you are concerned about the NAND flash interrupt, then things can actually be worse, if the Ethernet is given priority.
第二个问题是，当主线code 清除/套中断标志。通常这是用什么做这样，
The second issue is when mainline code clears/sets the interrupt flag. Typically this is done with something like,
mrs r9, cpsr
biceq r9, r9, #PSR_I_BIT
检查<一href=\"https://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=arch/arm/include/asm/irqflags.h;hb=HEAD\"相对=nofollow> 弓/ ARM /有/ ASM / irqflags.h 的在Linux源通过主线code使用的宏。 A <一个href=\"https://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=arch/arm/include/asm/bitops.h;hb=HEAD\"相对=nofollow>典型顺序是这样的，
lock interrupts;
manipulate some flag in struct;
unlock interrupts;
如果结构结果页面错误
可以推出一个非常大的中断延迟。中断将被屏蔽的网页错误处理程序的时间。
A very large interrupt latency can be introduced if that struct results in a page fault. The interrupts will be masked for the duration of the page fault handler.
在Cortex-A9有很多锁定免费指令可以prevent这个由<一个href=\"https://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=arch/arm/include/asm/atomic.h;hb=HEAD\"相对=nofollow>从未屏蔽中断;因为比 SWP / SWPB更好的汇编指令。这第二个问题是很像IRQ延迟由于 LDM / STM 型指令（这些只是运行时间最长的说明）。
The Cortex-A9 has lots of lock free instructions that can prevent this by never masking interrupts; because of better assembler instructions than swp/swpb. This second issue is much like the IRQ latency due to ldm/stm type instructions (these are just the longest instructions to run).
最后，大量的技术讨论将承担的零等待状态 RAM。它是可能的缓存将需要填补，如果你知道你的内存数据速率（也许2-4个机器周期），那么最坏的情况下code路径将通过这个繁殖。
Finally, a lot of the technical discussions will assume zero-wait state RAM. It is likely that the cache will need to be filled and if you know your memory data rate (maybe 2-4 machine cycles), then the worst case code path would multiply by this.
无论你是否有SMP中断处理，优先级的中断，并锁定免费主线取决于你的内核配置和版本;这些都为 OS问题即可。其他问题是固有的CPU / SOC的中断控制器，并以<一href=\"http://stackoverflow.com/questions/14674392/how-many-instructions-does-linux-kernel-need-in-order-to-handle-an-interrupt-on\">interrupt code本身。
Whether you have SMP interrupt handling, priority interrupts, and lock free main line depends on your kernel configuration and version; these are issues for the OS. Other issues are intrinsic to the CPU/SOC interrupt controller, and to the interrupt code itself.
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