操作系统导致的 irq 延迟是多少? [英] What is the irq latency due to the operating system?
问题描述
- 如何估计 ARM 处理器上的 irq 延迟?
- irq 延迟的定义是什么?
推荐答案
Mats 和 Nemanja 提供了一些关于 中断延迟.有两个是我要添加的另一个问题，除了 Mats 给出的三个问题.
Mats and Nemanja give some good information on interrupt latency. There are two is one more issue I would add, to the three given by Mats.
- 其他同时/几乎同时中断.
- 由于屏蔽中断而增加了操作系统延迟.这是 Mats 的回答，只是没有解释太多.
- Other simultaneous/near simultaneous interrupts.
- OS latency added due to masking interrupts. This is in Mats answer, just not explained as much.
如果是单核处理中断，那么当多个中断同时发生时，通常会有一定的解析优先级.但是，除非启用优先级中断处理，否则在中断处理程序中通常会禁用中断.因此，例如，发出信号并运行慢速 NAND 闪存 IRQ，然后发生以太网中断，它可能会延迟到 NAND 闪存 IRQ 完成.当然，如果您有优先中断并且您担心 NAND 闪存中断，那么如果优先考虑以太网，情况实际上会更糟.
If a single core is processing interrupts, then when multiple interrupts occur at the same time, usually there is some resolution priority. However, interrupts are often disabled in the interrupt handler unless priority interrupt handling is enabled. So for example, a slow NAND flash IRQ is signaled and running and then an Ethernet interrupt occurs, it may be delayed until the NAND flash IRQ finishes. Of course, if you have priorty interrupts and you are concerned about the NAND flash interrupt, then things can actually be worse, if the Ethernet is given priority.
第二个问题是当主线代码清除/设置中断标志时.通常这是通过类似的东西来完成的，
The second issue is when mainline code clears/sets the interrupt flag. Typically this is done with something like,
mrs r9, cpsr
biceq r9, r9, #PSR_I_BIT
检查 arch/arm/include/asm/irqflags.h 在 Linux 源代码中，用于主线代码使用的许多宏.典型序列是这样的，
lock interrupts;
manipulate some flag in struct;
unlock interrupts;
如果 struct 导致页面错误，则会引入非常大的中断延迟.中断将在页面错误处理程序期间被屏蔽.
A very large interrupt latency can be introduced if that struct results in a page fault. The interrupts will be masked for the duration of the page fault handler.
Cortex-A9 有很多无锁指令，可以通过从不屏蔽中断;因为比 swp/swpb 更好的汇编指令.第二个问题很像 ldm/stm 类型指令(这些只是要运行的最长指令)导致的 IRQ 延迟.
The Cortex-A9 has lots of lock free instructions that can prevent this by never masking interrupts; because of better assembler instructions than swp/swpb. This second issue is much like the IRQ latency due to ldm/stm type instructions (these are just the longest instructions to run).
最后，许多技术讨论将假设零等待状态 RAM.很可能需要填充缓存，如果您知道内存数据速率(可能是 2-4 个机器周期)，那么最坏情况下的代码路径将乘以这个.
Finally, a lot of the technical discussions will assume zero-wait state RAM. It is likely that the cache will need to be filled and if you know your memory data rate (maybe 2-4 machine cycles), then the worst case code path would multiply by this.
是否有SMP中断处理、优先级中断、无锁主线取决于你的内核配置和版本；这些是操作系统的问题.其他问题是 CPU/SOC 中断控制器和 中断代码本身.
Whether you have SMP interrupt handling, priority interrupts, and lock free main line depends on your kernel configuration and version; these are issues for the OS. Other issues are intrinsic to the CPU/SOC interrupt controller, and to the interrupt code itself.
这篇关于操作系统导致的 irq 延迟是多少?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
